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How do I add/register multiple axi interfaces in a zynq reference design?

조회 수: 1(최근 30일)
Hong Kim
Hong Kim 2018년 2월 1일
답변: Wang Chen 2021년 6월 30일
I have created a reference design, and registered a number of different zynq configurations correctly, and have been able to run simulink models in external mode with a bit stream loaded onto the FPGA portion of the zynq, but only with an axi bus enabled that the Simulink generated ipcore can connect to. As soon as I add a second axi interconnect, for use with other axi devices, the software model refuses to start and times out.
The following error only comes when I have more than 1 axi port:
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Attempting to establish connection with hostname '192.168.1.101' through port 17725. Error occurred while executing External Mode MEX-file 'ext_comm': Failed to connect to the target. Possible reasons for the failure: a) The target is not switched on. b) The target is not connected to your host machine. c) The application for the model is not running on the target. You might have clicked the Stop button. If the Run button is not dimmed, click it. Otherwise, click the Build button, which downloads and runs your application on the target.
Caused by: An error occurred attempting to open an rtIOStream. More detail may be reported in the MATLAB command window
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In my registration file, I have the following snippet of code in plugin_rd.m to attempt to add two clocks, as well as two axi. I'd like to register both, but the HDL workflow adviser does not distinguish between one axi slave port, and the other. Nor does it allow us to choose which clock the Axi component will be driven by:
--------------------------------------------------------------------- %% Add interfaces % add clock interface hRD.addClockInterface( ... 'ClockConnection', 'clk_wiz_0/clk_out1', ... 'ResetConnection', 'proc_sys_reset_0/peripheral_aresetn'); hRD.addClockInterface( ... 'ClockConnection', 'clk_wiz_0/clk_out2', ... 'ResetConnection', 'proc_sys_reset_0/peripheral_aresetn'); % add AXI4 and AXI4-Lite slave interfaces hRD.addAXI4SlaveInterface( ... 'InterfaceConnection', 'axi_interconnect_0/M00_AXI', ... 'BaseAddress', '0x40010000', ... 'MasterAddressSpace', 'processing_system7_0/Data'); hRD.addAXI4SlaveInterface( ... 'InterfaceConnection', 'axi_interconnect_0/M00_AXI', ... 'BaseAddress', '0x40010000', ... 'MasterAddressSpace', 'processing_system7_0/Data');
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Matlab version: 2017a Vivado version: 2016.2

답변(1개)

Wang Chen
Wang Chen 2021년 6월 30일
Hi Hong,
HDL Coder generated IP core can only have one AXI4 slave interface. In latest version of MATLAB, HDL Coder will error out when you running hRD.addAXI4SlaveInterface() twice in the reference design definition file.
If you want to connect two different AXI4 master device to the HDL Coder generated IP core, you could use an AXI Interconnect IP in Vivado. Two seperate AXI4 master device can connect to the AXI Interconnect IP, and then the AXI Interconnect IP can connect to the HDL Coder generated IP core. In this way both AXI4 master device can access the same IP Core.
Thanks,
Wang

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