All filter coefficients not used in HDL code
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I have generated a VHDL code for 6 coefficient symmetric Digital Filter using HDL Coder.
Since it is a symmetric filter, only coeff1, coeff2, coeff3 are defined in generated HDL code.
I am not able to understand where coeff2 is being used in calculating filter output. The use of coeff1 and coeff2 is clear. The rest of the code is also well understood
What is the meaning of the following line:
product2 <= resize(tapsum_mcand_1(11 DOWNTO 0) & '0' & '0', 14);
As i understand coeff2 should have been multiplied with tapsum_mcand_1 to generate product2:
The generated code is given below:
-- ------------------------------------------------------------
--
-- File Name: hdlsrc\filtering\Digital_Filter
-- Created: 2017-10-31 09:14:58
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- ------------------------------------------------------------
--
--
-- ------------------------------------------------------------
--
-- Module: Digital_Filter
-- Source Path: /Digital_Filter
--
-- ------------------------------------------------------------
--
-- HDL Implementation : Fully parallel
-- Multipliers : 3
-- Folding Factor : 1
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY Digital_Filter IS
PORT( clk : IN std_logic;
enb : IN std_logic;
reset : IN std_logic;
Digital_Filter_in : IN std_logic_vector(13 DOWNTO 0); -- sfix14_En13
Digital_Filter_out : OUT std_logic_vector(13 DOWNTO 0) -- sfix14_En13
);
END Digital_Filter;
----------------------------------------------------------------
--Module Architecture: Digital_Filter
----------------------------------------------------------------
ARCHITECTURE rtl OF Digital_Filter IS
-- Local Functions
-- Type Definitions
TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF signed(13 DOWNTO 0); -- sfix14_En13
-- Constants
CONSTANT coeff1 : signed(13 DOWNTO 0) := to_signed(3072, 14); -- sfix14_En10
CONSTANT coeff2 : signed(13 DOWNTO 0) := to_signed(4096, 14); -- sfix14_En10
CONSTANT coeff3 : signed(13 DOWNTO 0) := to_signed(6144, 14); -- sfix14_En10
-- Signals
SIGNAL delay_pipeline : delay_pipeline_type(0 TO 4); -- sfix14_En13
SIGNAL Digital_Filter_in_regtype : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL tapsum1 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_1 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_temp : signed(14 DOWNTO 0); -- sfix15_En13
SIGNAL tapsum_mcand : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL tapsum2 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_2 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_3 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_temp_1 : signed(14 DOWNTO 0); -- sfix15_En13
SIGNAL tapsum_mcand_1 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL tapsum3 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_4 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_5 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_temp_2 : signed(14 DOWNTO 0); -- sfix15_En13
SIGNAL tapsum_mcand_2 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL product3 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL mul_temp : signed(27 DOWNTO 0); -- sfix28_En23
SIGNAL product2 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL product1_cast : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL product1 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL mul_temp_1 : signed(27 DOWNTO 0); -- sfix28_En23
SIGNAL sum1 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_6 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_7 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_temp_3 : signed(14 DOWNTO 0); -- sfix15_En13
SIGNAL sum2 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_8 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_cast_9 : signed(13 DOWNTO 0); -- sfix14_En13
SIGNAL add_temp_4 : signed(14 DOWNTO 0); -- sfix15_En13
SIGNAL output_typeconvert : signed(13 DOWNTO 0); -- sfix14_En13
BEGIN
-- Block Statements
Delay_Pipeline_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
delay_pipeline(0 TO 4) <= (OTHERS => (OTHERS => '0'));
ELSIF clk'event AND clk = '1' THEN
IF enb = '1' THEN
delay_pipeline(0) <= signed(Digital_Filter_in);
delay_pipeline(1 TO 4) <= delay_pipeline(0 TO 3);
END IF;
END IF;
END PROCESS Delay_Pipeline_process;
Digital_Filter_in_regtype <= signed(Digital_Filter_in);
add_cast <= Digital_Filter_in_regtype;
add_cast_1 <= delay_pipeline(4);
add_temp <= resize(add_cast, 15) + resize(add_cast_1, 15);
tapsum1 <= add_temp(13 DOWNTO 0);
tapsum_mcand <= tapsum1;
add_cast_2 <= delay_pipeline(0);
add_cast_3 <= delay_pipeline(3);
add_temp_1 <= resize(add_cast_2, 15) + resize(add_cast_3, 15);
tapsum2 <= add_temp_1(13 DOWNTO 0);
tapsum_mcand_1 <= tapsum2;
add_cast_4 <= delay_pipeline(1);
add_cast_5 <= delay_pipeline(2);
add_temp_2 <= resize(add_cast_4, 15) + resize(add_cast_5, 15);
tapsum3 <= add_temp_2(13 DOWNTO 0);
tapsum_mcand_2 <= tapsum3;
mul_temp <= tapsum_mcand_2 * coeff3;
product3 <= mul_temp(23 DOWNTO 10);
product2 <= resize(tapsum_mcand_1(11 DOWNTO 0) & '0' & '0', 14);
product1_cast <= product1;
mul_temp_1 <= tapsum_mcand * coeff1;
product1 <= mul_temp_1(23 DOWNTO 10);
add_cast_6 <= product1_cast;
add_cast_7 <= product2;
add_temp_3 <= resize(add_cast_6, 15) + resize(add_cast_7, 15);
sum1 <= add_temp_3(13 DOWNTO 0);
add_cast_8 <= sum1;
add_cast_9 <= product3;
add_temp_4 <= resize(add_cast_8, 15) + resize(add_cast_9, 15);
sum2 <= add_temp_4(13 DOWNTO 0);
output_typeconvert <= sum2;
-- Assignment Statements
Digital_Filter_out <= std_logic_vector(output_typeconvert);
END rtl;
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채택된 답변
Bharath Venkataraman
2017년 11월 2일
편집: Bharath Venkataraman
2017년 11월 2일
coeff2 has been recognized as a power of 2, and so implemented using a shift. No multiply is needed for this operation.
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Bharath Venkataraman
2017년 11월 3일
Also, you can use CSD or Factored CSD implementations to remove all multipliers and do the entire operation in shift and add logic if you so prefer.
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