Why simple digital intergrator can not work in HDL Coder

Hi,,

I can not get the hdl code when I use new native floating point function, there is only one block:

Discrete-Time Integrator

The erro msg is :

Cannot allocate 12 delays for untitled8/Subsystem/XeAccum1/Add1 in the native floating-point mode.

It also happens when I use a delay and a adder to build an intergrator myself.

The slx file is attached.

Answer 1

[Hongyin]

It seems because the feedback to the adder, the adder and delay works fine when they are not in the feedback loop

Answer 2

[Tim McBrayer]

The Native Floating Point implementation for the DTI uses addition, which is pipelined by default. You can change the NFP settings to use zero latency implementations, which avoids the problem but may not meet your timing requirements. If you set the model to oversample at 12x (HDL Code Generation > Global Settings > Clock Settings > Oversample factor), this will allow the 12-cycle latency of the adder in the feedback loop to be counteracted by the faster clock rate, and you can generate HDL code successfully.