hdl coder stateflow bit concatenation

Hi, I am using matlab R2015b with staflow and hdl coder to create VHDL code.

I need to do something like this in vhdl in a matlab function residing in a stateflow chart that hdl coder understands and can compile to vhdl and I can't figure it out.

a : std_logic_vector(2 downto 0);
b, c, d : std_logic;
a <= b & c & d;

Thanks for the help, Amish

Answer 1

[Tim McBrayer]

To concatenate fixpt variables being used as bit fields, use the MATLAB bitconcat function. To extract a range of bits from a larger word you can use bitsliceget.

There are Simulink blocks in the HDL Coder library, in "HDL Operations" that implement this functionality directly in Simulink.

[Amish Rughoonundon]

Thanks, that was the answer.