Timing constraints file for hdl coder
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HI; I am designing a communication model in Matlab HDL coder (system generator) but I got the problem is a missing constraints file for timing. do any one have the solution for this problem?
sample time=1 for all components.
Regards
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Rakesh Chavan
2016년 3월 16일
Hi,
When you say System Generator are you referring to the Xilinx system generator block. If so when you get the error is it caused by the System generator block? It might be a good idea to check with Xilinx as well if the Xilinx system generator block is throwing the error message.
Can you provide an image of the screenshot of the error message, that might help in understanding the issue you are facing.
Hope this helps
regards
Rakesh
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Kiran Kintali
2021년 5월 22일
편집: Kiran Kintali
2021년 5월 22일
In MATLAB to HDL GUI project you can include additional project files related to constraints.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/626573/image.jpeg)
Add these two files in the location where your MATLAB code and HDL Coder project files are located.
insert_timing.tcl
add_file {../../../../clock_constraint.xdc}
clock_constraint.xdc
create_clock -name MWCLK -period 4.545 [get_ports clk]
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