We'd like to use the standard Unit Delay block in the Simulink HDL-Coder. As a minimal example we created an Atomic Subsystem, only consisting of a single Unit Delay block.
The simulation worked as expected: The input signal was delayed by one time step.
The model was tested on our Zedboard Zynq-7000. The subsystem ran on the FPGA. However, in contrast to the simulation, the unit delay did not seem to do anything at all, as the output signal was exactly the same as the input signal.
We use Matlab R2015b with Vivado 2014.4.
The Simulink model was attached.