Can anyone explain the relationship between simulink sampling time and real world clock in FPGA?

Hello.

Can anyone explain the relationship between simulink sampling time and real world clock in FPGA? I'm working with FPGA Cyclone IV, Matlab 2014b.

Answer 1

[Ganesh Gaonkar]

Hi,

This example from MathWork's HDL Verifier Toolbox can give you a good idea on the relation between Simulink Sample Time and FPGA clock ticks.

[Yeung Pok Nga]

This page doesn't exist anymore, could you please provide a different link? Thank you