Issue in generating RxvalidIn signal in HW/SW Co-design QPSK Transmitter and Receiver

Hi Matlab Team,

we followed the example design HDL QPSK Transmitter and Receiver. We sucessfully generated the HDL code for the TX & RX block and we observe the design workflow like input bits packetized and transmitted in frame based.

In Loop Back Mode :

TX module outputs TXDataOut[15:0] , TXvalidOut signal is directly connected with the RXdataIn[15:0] ,RXvalidIn. since its a frame based model the TXvalidOut signal is generated accordingly so, its sync with RX module and works fine able to receive the correct data.

Now, we want to implement this design in hardware so we follow the HW/SW co-design QPSK Transmitter and Receiver. The same optimized QPSK TX and RX block is used in this design. If we connect the QPSK TX module output to AD9364 after bit reduction from 16 to 12 bit we can able to see the output in spectrum a modulated QPSK waveform. But the problem is while implemeting the QPSK RX module it primilary requires RXdataIn[15:0] and RXvalidIn signal. The AD9364 will give the 12bit IQ sample of QPSK modulated received signal so issue is what we have to do the RXvalidIn.

If we make the RXvalidIn as default high we did'nt received demodulated bits correctly.

Connecting the HDL QPSK with axi_ad9361 IP core:

In this design the RXvalidIn is coming from the IP core but the RXvalidIn signal is not generated based on frame its generated based on RXframe so, how to make the RX module to work to demodulate correct data.

These are the key points and results were observed from the matlab simulink and HDL file (axi_ad9361 Ip core). we don't how to generate the RxvalidIn signal based on the incoming frame to make the rx module to work.

Hardware : ADRV9364-z7020 EVM board.

Answer 1

[Karthik Akula]

The Rx operates with a continuously asserted stream valid signal, even though the data structure is packetized. It includes a synchronization mechanism to automatically determine packet boundaries. Even in a back-to-back connection, the first sample is not treated as the start of a frame. So i suspect something else as I expect the 'always high' of Rx valid to work as long as it receives the samples from ADC

Please try following the workflow in the example and see it works fine. Make sure you use the axi_ad9361 IP Core to interface the ADC and the Rx as done automatically in the workflow. They are designed for the purpose of coordinating the master slave AXI4-Stream Protocol.

The documentation shows the results of HW simulation on ZC706. you can try ZCU102. or any support package provided platform for IIO radio in the IP Core generation workflow in the HDL workflow advisor.

[kalainan]

Hi Karthik Akula,

we have integrated the QPSK Modulation and Demodulation block with the axi_ad9361 ip core. The previous valid signal issue ressloved here. But we did'nt get any output from the Demodulation block.

Test Procedure we follow :

Sampling rate for AD9364 is 20MHz. we working with AD9364 so it is 1R1T mode so the clock from the axi_ad9361 ip core clock is divided by 2 in your case so 10MHz is given to the both MOD & DE-MOD HDL QPSK block.

Block connection we follow :

a) Transmitter side

QPSK modulation block -> DAC FIFO -> axi_ad9361 ip core

b) Receiver side

axi_ad9361 ip core -> ADC FIFO -> QPSK demodulation block. This block connections are recommended by the Analog device to meet timing constrains of axi_ad9361 ip core.

Both the FIFO block will accept the 16 bit only but the AD9361 will accept 12 bit for that they have neglating the 4bit lsb for transmitter side (DAC FIFO ) and 4bit sign extension in ADC FIFO side. we have tried two approach

1. First the DAC side dividing the QPSK modulated 16bit data by 16 from this we converting 2^16 to 2^12 after that append 4 bit zeros in lsb and given to DAC FIFO in TX side. while in RX side remove 4bit MSB[15:12} and mutliply the 12 bit[11:0] * 16 to get back the 16 bit modulated data.
2. Second approach no division or mutilpication done directly 16 bit send to DAC FIFO and 16 bit data from ADC FIFO send to the QPSK Demodulation block.

Both approach is did with the RF LOOPBACK & DIGITAL LOOPBACK but we did'nt get any output only we absorb the pulse in ctrlOut_endOut signal all other signals are zero. what will be the issue ?.

At what condition the QPSK Demodulator block will work like this?