FIL Error: "Did not receive version information" with connection that works in Vivado

Hello,

I am having an issue with the FPGA-in-the-Loop (FIL) feature in HDL Coder.

1. My Environment:

• MATLAB Version: R2024a
• Vivado Version: 2024.2
• FPGA Board: Digilent Arty Z7-20

2. My Goal:I want to verify a Simulink model on my FPGA hardware using the FIL workflow.

3. The Problem:The HDL Workflow Advisor completes the build process (through step 4.2) successfully and generates the green FIL block. However, when I run the simulation in a Simulink model containing this FIL block, it fails to connect to the hardware and gives the following error:

Error: Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.

4. Important Context:I have verified that the physical connection itself is working correctly. Using the exact same PC, USB cable, and FPGA board, I can successfully connect to the board, recognize the device, and program it using the Vivado Hardware Manager. This suggests the issue is not with the hardware, cable, or physical ports.

5. What I Have Already Tried:I have attempted the following solutions, but the error persists:

• Running MATLAB as an Administrator.
• Explicitly setting the tool path using the hdlsetuptoolpath command.
• Manually starting vivado_hw_server from the Vivado Tcl Shell and telling MATLAB to connect to it using setenv('MW_HW_SERVER_PORT', ...).
• Rebooting the PC and reconnecting the USB cable to different ports.

Could you please advise on any other potential causes or troubleshooting steps for this issue?

Thank you.

Answer 1

[Nivedita]

Hello,

You can follow the troubleshooting steps mentioned in the official documentation to resolve the issue:

https://www.mathworks.com/help/releases/R2024a/hdlverifier/ug/troubleshooting-fil.html

You can follow this thread in the community and try to follow any of the steps that may have seemed to work for others in resolving the exact issue you are facing:

https:/www.mathworks.com/matlabcentral/answers/40145-hdl-verifier-and-fpga-in-the-loop

Answer 2

[Rito Sakima]

Thank you very much.

The issue has been resolved thanks to you. I really appreciate your help.