Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?

Dear all,

I am using SoC Blockset for a simple design for AMD Zynq Ultrascale+ ZCU111 evaluation board.

If I understand it correctly, the SoC Blockset add-on uses HDL coder to generate code for FPGA part of the SoC, but this is done through the SoC Builder interface, in which there are much less flexibility then in HDL coder. Does SoC Builder do some FPGA resource optimizations for build? How can I see the resource mapping? Can I change the mapping manually (for a better optimization, e.g.) or is it not possible to make a better mapping then the one produced automatically?

Thank you for your answers!

Answer 1

[Chandra Adusumalli]

SoC Builder considers the hdl code generation settings in the FPGA model configuration. Please refer to the following link for more information .

Model Configuration Parameters: HDL Code Generation - MATLAB & Simulink

[Sergei]

Thank you a lot! I was wondiring for a while, whether HDL code generation parameters set in the Top model are considered while HDL code generation or those set in FPGA model. You answered this question also)

[Sergei]

I have read the article, but I still cannot see where to find resource mapping report: is there a way to see where each of the components is mapped to on the HW? Is there a way to change this mapping? I am asking because in Vivado after design Synthesis there is a possibility to do so. In the report generation pane I only found report to resource optimization and report on optimization. Thank you!

Answer 2

[Kiran Kintali]

For working with the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board using HDL Coder, MathWorks provides detailed documentation and workflows. :

Create RFSoC HDL Coder Models: This example walks you through using the Zynq RFSoC Template Builder tool to create HDL Coder models for the ZCU111 board. It includes configuration options for ADC/DAC interfaces, clock domain settings, and reference design customization. See documentation.

Zynq UltraScale+ RFSoC Design with MATLAB and SimulinkThis broader resource covers system development, simulation, and deployment workflows using MATLAB and Simulink for Zynq UltraScale+ RFSoC devices, including the ZCU111. It includes examples, videos, and tools for HDL and embedded C code generation. You can explore the solution.

Regarding help setting up a model or generating HDL code for a specific application on the ZCU111 board

1. https://www.mathworks.com/help/hdlcoder/xilinxzynq7000/ug/create-rfsoc-hdl-coder-models.html
2. https://www.mathworks.com/solutions/fpga-asic-soc-development/rfsoc.html

Unless you need to model and simulate the hardware/software interfaces, you can remain at the algorithmic level and use the base HDL Coder targeting features. For more details on the benefits of transitioning to an SoC model and to determine whether your original model requires these capabilities—please refer to the attached HW_SW_Workflow_Unified.pdf document for more details.

[Sergei]

Thank you a lot for this list of resources! This definetely will be read by me and I hope it will help me in future use of MATLAB for SoC design.