Simulation initialization error with Xilinx reinterpret block for Fix54_36 output

I have set up the following simple simulation, where a UFix54_0 constant is fed into a reinterpret block, which outputs a signed, two's complement number of form Fix54_36:

Here are the settings for teh system generator:

When I run the simulation I receive the following error:

Error loading /users/wklahold/.Xilinx/Sysgen/lin64/cache5/base/d481/9d225652abd1457877dbc15a16bd/xlsim.so

Error occurred during "Simulation Initialization".

This appears to occur only for an input bitwidth 54 and output binary point 36. If I change either the input bitwidth or the output binary point, the simulation completes without error. Much appreciated if anyone can figure out what's going on.