Represent std_logic_vector in Simulink
조회 수: 3 (최근 30일)
Does SIMULINK support creation of typical HDL data types or only MATLAB types (e.g. UINT32, FI, etc.)? Some of the inputs to my system do not fall neatly into power-of-2 variable sizing and I would like to be able to create something equivalent to std_logic_vector (13 downto 0) in SIMULINK. Even if I have to somehow create the datatype from scratch, is this possible?
I want to be able to use this datatype and assign it to my ports as their datatype.
Kiran Kintali 2023년 9월 7일
편집: Kiran Kintali 님. 2023년 9월 8일
HDL Coder supports fixed point data types with integer lengths ranging from 1 to 128 bits.
During the HDL code generation process, these map to the std_logic_vector type (typically used for arrays of std_logic variables and signals in VHDL).
Try HDL Code generation from some of example MATLAB Code and Simulink models foudn here..
You can browse through the code samples in the HDL Coder documentation to get an idea of the std_logic and std_logic_vector types generated.
y : OUT std_logic_vector(32 DOWNTO 0) -- sfix33_En20