Native floating-point latency and adding delay block.

for implementing this Math equation

why adding delay block (Z-11) change the numeric value from -1.337 to only -1 ?

how can I solve this problem to get the same value before delay block without changing?

thanks

[Walter Roberson]

The -1.667 and -1 are effectively the state of the signal at different times. The version is 11 time steps delayed from the first one -- and so shows the signal from 11 time steps earlier.

[mahmoud ebead]

thanks for your reply ,but this delay block Z-11 is required by latency consideration with native floating point (HDLcoder)

,the problem that adding it give me numerical mistakes as showen in the figure.

Any assistent you can provide to solve this problem will be greatly apprecieated

thanks

Answer 1

[Kiran Kintali]

You can just model the math and let HDL Coder figure out how to pipeline the design.

    

>> makehdl('dut_nfp/Subsystem')
### Working on the model dut_nfp
### Generating HDL for dut_nfp/Subsystem
### Using the config set for model dut_nfp for HDL code generation parameters.
### Running HDL checks on the model 'dut_nfp'.
### Begin compilation of the model 'dut_nfp'...
### Working on the model 'dut_nfp'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 54 cycles.
### Working on... GenerateModel
### Begin model generation 'gm_dut_nfp'...
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Generated model saved at hdlsrc\dut_nfp\gm_dut_nfp.slx
### Delay absorption obstacles can be diagnosed by running this script: hdlsrc\dut_nfp\highlightDelayAbsorption.m
### To clear highlighting, click the following MATLAB script: hdlsrc\dut_nfp\clearhighlighting.m
### Begin VHDL Code Generation for 'dut_nfp'.
### Unused logic removed during HDL code generation. To highlight the logic removed, click the following MATLAB script: highlightRemovedDeadBlocks.m
### To clear highlighting, click the following MATLAB script: clearHighlightingRemovedDeadBlocks.m
### Working on dut_nfp/Subsystem/nfp_div_single as hdlsrc\dut_nfp\nfp_div_single.vhd.
### Working on dut_nfp/Subsystem/nfp_sub_single as hdlsrc\dut_nfp\nfp_sub_single.vhd.
### Working on dut_nfp/Subsystem as hdlsrc\dut_nfp\Subsystem.vhd.
### Generating package file hdlsrc\dut_nfp\Subsystem_pkg.vhd.
### Code Generation for 'dut_nfp' completed.
### Generating HTML files for code generation report at dut_nfp_codegen_rpt.html
### Creating HDL Code Generation Check Report Subsystem_report.html
### HDL check for 'dut_nfp' complete with 0 errors, 0 warnings, and 2 messages.
### HDL code generation complete.
>> 

The generated HDL code contains the necessary latency inserted to pipeline the floating point operators; the latency is automatically balanced.

You can check the generated model to visualize the latency insertion done for the various floating point operators..

See the attached example for additional details.