timing control module _tc.v have failed path to other module

my HDL code from HDL codeGen has timing error. Some of the failed path are from module _tc.v to other modules.

in the tc.v module, it generates clock enable signal enable_1_8_1 which is the output from phase_1 && clkEN

enb_1_1_1_1 = phase_1 & clk_EN;

should be enb_1_1_1_1 registerted to solve the timing error?