Efficient packing of data for BlockRAMs, UltraRAMs
조회 수: 8 (최근 30일)
I have a system where there's four channels of 18-bit data processed simultaneously and written to a RAM as 4096 words x 4 channels of data. HDL Coder seems to want to instantiate four separate RAMs (appears that way in the Verilog), and Vivado shows this too.
I'd like to see the four channels packed into a 72-bit word and written to one location in an UltraRAM. I specified "ultra" for the RAMDirective, and this "works" - the netlist shows four UltraRAMs in use, so at least we've got UltraRAMs.
But how do I get the data packed into a single 72-bit word? Is that something I need to do in the Simulink diagram?
Ryan Baird 2023년 3월 22일
편집: Ryan Baird 님. 2023년 3월 22일
The RAM block interprets vectors of data to mean you want separate RAM banks. In order to store and retreive the data as a single value, you currently need to combine the data before writing and separate the data after reading outside of the RAM block. The easiest way I'm aware of to do this is with the Bit Concat and Bit Slice blocks. You could use a Bit Concat block before the RAM block to combine the data, and use Bit Slice blocks after the RAM block to separate the read data back into 4 different values.