How to convert the Simulink project to VHDL code?
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Maneesha Shibu 2023년 2월 16일
댓글: Kiran Kintali 2023년 3월 10일
I have created a digital down converter in simulink and I want to convert it into VHDL Code.But in this I can only convert one subsytem to VHDL rest of them is getting one or another type of errors.
The errors are:
call to function cordicrotate is not supported
comment out the block
set the multitask data transfer and singletask data transfer to error on diagnostics additionaly in solver pane,set solver type to fixed-step and in the solver details-tasking and samle time options group selet 'treat each discrete rate as a separate task'
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Bharath Venkataraman 2023년 2월 24일
You can run the hdlsetup function on the model to set the parameters of the model to common default values for HDL code generation.
This example shows how to build a DDC for HDL code generation and may give you some insight as well.
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Kiran Kintali 2023년 2월 24일
편집: Kiran Kintali 2023년 2월 24일
Implement Digital Downconverter for FPGA
This example shows how to design a digital downconverter (DDC) for radio communication applications such as LTE, and generate HDL code.
Are you implementing these modules using custom subsystems?
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Kiran Kintali 2023년 3월 10일
Can you reach tech support or share your model with the reproduction steps?
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