Why do I get the error: " FIL cosimulation failed: the output does not match the expeced result" when I run FPGA-in-the-Loop Test?

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Hi, iI m trying to run the fpga in the loop test inside HDL coder. The HDL code was generated by a script in matlab (I didn't use a model in Simulink). I selected the board Xilinx Virtex Ultrascale VCU118 and the connection is JTAG ( my board has an onboard Digilent USB-JTAG module) . Then I added Vivado tool to MATLAB search path. When I tried to validate FPGA board, I obtain this error: "FIL cosimulation failed: the output does not match the expeced result ".
How can I fix it? Thank you.
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답변(1개)

Kiran Kintali
Kiran Kintali 2022년 9월 7일
If the HDL Code you are running is run with is generated from HDL Coder and is not matching the MATLAB or Simulink testbench then this is not an expected message. You can contact technical support with reproduction steps.

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