Problem in generating reusable Verilog code using Simulink HDL Coder

조회 수: 4(최근 30일)
I am trying to generate a reusable Verilog code for an atomic Masked subsystem using Simulink HDL Coder . In my midel there are two such subsystems used. Both the subsystem is same except there mask parameter value. But while generating Verilog Code, it is generating one file for each subsytem.
Both the subsytem is linked to a library (User defined) block.
The DefaultParameterBehavior Configuration Parameter is set to Inlined. The mask parameters are non tunable. The Generate parameterized HDL code from masked subsystem option is enabled.
I am sharing the generated Verilog code of the top module that instantiates both the subsystem blocks.
I need that it will generate only one file (constant1.v) instead of two and instatntitaed using only constant1.
constant1 #(.a(0),
u_constant1 (.Out1(constant1_out1), // uint32
.Out2(constant1_out2), // uint32
.Out3(constant1_out3), // uint32
.Out4(constant1_out4) // uint32
constant2 #(.a(0),
u_constant2 (.Out1(constant2_out1), // uint32
.Out2(constant2_out2), // uint32
.Out3(constant2_out3), // uint32
.Out4(constant2_out4) // uint32


Kiran Kintali
Kiran Kintali 2022년 7월 31일
Feel free to reach out to technical support for this question.
You may want to try to use the new subsystem reuse algorithm available with HDL Coder
hdlset_param('myHDLModel', 'SubsystemReuse', 'Atomic and Virtual')
  댓글 수: 1
Arpita 2022년 7월 31일
I have already chosen this options in the HDL code generation option. Though in the subsystem parameter I have enabled the option " Treat this as atomic subsystem" .

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