Code Generation for d flipflop

Hi team,

i have D Flipflop in my simulink model ,when i am trying to generate vhdl code from the model i am getting the error like " Input port 'D' must not have 'Latch input by delaying outside signal' selected for HDL code generation".Please suggest me how i can proceed further by resolving this error.

Best Regards,

Rajini

Answer 1

[Bharath Venkataraman]

Do you really need to model the D Flip Flop (especially the clock)? If not, I suggest using the Delay block (with enable if you need it). The generated HDL will have a clock port you can drive in the hardware.

[Rajini Gajula]

Hi Sir,

Will you please eloborate more on this,how i can proceed with Delay as i have 3 inputs enable,clr and D input to D flipflop.

[Bharath Venkataraman]

The Delay block has options to add enable, reset inputs ports and the data input, which I think should meet your needs.

If all you are trying to model is a delay by a clock and the ability to do synchronous reset, and enable, the delay block will work for you.

You can add in the state control block (synchronous mode) to model the HDL behavior for enable & reset.

[Rajini Gajula]

Hi Sir,

According to our requirement thorugh D flip flop i am expecting latching action to takes place but if i am using delay block ,i am unable to get the latching ,please suggest me how else i can proceed on this.

[Bharath Venkataraman]

Here is a simple model that shows how the delay block works.

[Rajini Gajula]

Hi Sir,

I am unable to open the model in the given version,will u please export this to R2018b version and share again.

Thanks in advance,

Rajini.

[Bharath Venkataraman]

The model for 18b is attached - hope this works.

[Rajini Gajula]

Thank you so much sir,it is working.