Vivado ML Editions is the FPGA EDA tool suite from AMD/Xilinx based on machine-learning optimization algorithms, as well as advanced team-based design flows, for significant design time and cost savings. Vivado ML Editions claims to deliver 5x or more faster compile time and breakthrough quality of results (QoR) improvements on average of 10% for complex designs, compared to the current Vivado HLx Editions.
HDL Coder™ enables high-level design for FPGAs, SoCs, and ASICs by generating portable, synthesizable Verilog® and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. You can use the generated HDL code for FPGA programming, ASIC prototyping, and production design. You can optimize for speed and area, highlight critical paths, and generate resource utilization estimates before synthesis.
HDL Coder generated RTL (VHDL and Verilog) should be compatible and further optimized by the Vivado ML FPGA tool suite.
