HDL Verifier Max Bit Width Using System Object
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I have a SystemVerilog HDL module that I am trying to test with HDL Verifier. The module takes in a packed 2-D array of 16x32 elements. This means that one of the input ports requires 512 bits, but when I try to send an FI object in that's 512 bits wide using the step function, I get an error that the max fixed point word length is 128 bits.
The only workaround that I know is to fall back to the old method of using raw bit strings and a callback function. But that's not ideal as I hope to be able to use FIL later which appears to exclusively use the System object.
I tried using an unpacked array, but that didn't seem to work with HDL verifier at all.
Is there a way to accomplish this with the System object?
Thank you!
-David
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YP
2021년 11월 12일
Hi David,
Do you mean FIL system object? FIL doesn't support sytem verilog HDL. Can you attach your code and elaborate your workflow?
And I don't understand what you mean by 'old method of using raw bit strings and a callback function' either.
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Marc Erickson
2021년 11월 12일
The flattening would requiring splitting as well, to something like:
input wire [15:0] [7:0] input_elements_1;
input wire [15:0] [7:0] input_elements_2;
etc.
Frames are what you suspect: they represent a collection of samples over time. We have not deprecated frames, just the use of the property to designate whether it is a frame or a multi-dimensional sample. Unfortunately, this is exactly the differentiation you are looking for.
So, currently the only workaround to supporting N-D signals is to:
- use Simulink cosim and FIL
- wrap your Verilog in VHDL
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