No of Pipeline Stages in Verilog coming from an m file (or latency)

How does one find how many pipeline stages exist in the verilog file. Example, run the mdhlc_sobel filter example from the web site and just pushing the default buttons in work flow advisor I get the design to run fast exceeding my system requirements. However, I dont know how many pipeline registers were put in there. The verilog code seems to show 12 - 15 or more stages (not sure) but I cannot tell what the latency will be. Also, it is hard to see the structure/data flow in the verilog code due to the number of times variables change names and then are pipelined. Version is 2014a.

Answer 1

[Tim McBrayer]

The short answer is that the conversion of the original untimed MATLAB code to sequential HDL requires multiple clock cycles to implement. This is just part of the nature of the algorithm, so will vary depending upon the particular design. I'm not familiar with this particular example so I can't say what causes the code to require conversion to sequential form like this.

For your question #1: HDL Coder is indicating that the generated HDL contains a latency of n cycles. With no explicit pipelining, the conversion of the algorithm from untimed MATLAB code to sequential HDL code requires n cycles to complete in HDL. You do not need to add explicit pipelining unless desired. The delays are not pipeline registers per se, but are required for the algorithmic conversion.

Question #2 is a more generalized FPGA design question. The 'correct' answer may depend upon your algorithm, your target device, synthesis tool, whether HDL Coder is using Distributed Pipelining, and many other factors. I don't think that there is a hard and fast answer to this other than "whatever works well for your design environment".

Answer 2

[Tim McBrayer]

The latency of a HDL Coder design should be output onto the Workflow Advisor output pane, on the HDL Code Generation tab. It will appear something like this:

 ### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
 ### Output port 0: 3 cycles.
 ### Output port 1: 3 cycles.

[Arun]

Tim, Thanks. Yes, I did see that (I have output port: 10 cycles) but was not expecting it. I had Register Inputs and Register Outputs checked, Distribute pipeline registers unchecked, Distribute Pipeline Registers unchecked, Preserve Design Delays unchecked and Input Pipelining and Output Pipeling both set to zero, and Loop Optimization as none. So I expected two register stages only and expected the design to run "really slow". Instead, the design ran "really fast" under Quartus. My message is the same as what you have above "DUT requires an initial pipeline..." Question 1) did hdl coder automatically put in pipelines even if you dont explicitly ask for it or is the message a warning saying re-run the design with an explicit setting of 10 (in this case) pipeline stages, 2) when should one use input pipeline vs output pipeline.