Is HDL Coder capable of generating configurable code?

For example mapping, system variable into GENERIC in VHDL, and PARAM in Verilog?

Answer 1

[Wang Chen]

Hi Ethan,

GENERIC/PARAM is supported by HDL Coder when you use "Generate parameterized HDL code from masked subsystem" feature.

HDL Coder can generate one HDL file for multiple masked subsystems with different values for tunable mask parameters. The coder automatically detects atomic subsystems with tunable mask parameters that are shareable, and then generate GENERIC/PARAM for the parameters. Inside the subsystem, you can use the mask parameter only in the Constant and Gain block, and the data type of the multiple instances of the parameter must be the same.

Please see following documentations for details: http://www.mathworks.com/help/hdlcoder/ug/hdl-code-generation-pane-global-settings.html#bs2y2zq http://www.mathworks.com/help/hdlcoder/ug/generating-reusable-code-for-atomic-subsystems.html#bs6km_v-1