Control the gain variable inside the generated IP block

Hello,

I have a simulink block which generates the signal at a given frequency. The output of the signal generator is fed into Gain block and later some filters and the output at the last. These blocks are made into subsystems which has signal input and output.

My question is when i convert this simulink block into Xilinx IP using HDL code generator, I get one AXI Lite interface. I have additionlly added AXIS stream as well. so i can control my stream output based one values written to AXI lite from processor. Now i want to change the gain of the sinmulink model inside the subsystem.

Is there any way i can do that? Like i have 100 gain values which needs to be changed and i dont want everytime to go to simulink , change the gain value and generate IP again.

Is it possible to change via AXI lite?or any other mean? Any suggestions is appreciated.

IP core generation example.

https://www.mathworks.com/help/supportpkg/xilinxzynq7000/ug/generate-an-ip-core-for-zynq-7000-platform-from-matlab.html#bujzgzw

Thank you

Answer 1

[JT Ferrara]

Hi Anoop,

This can be accomplished in two different ways:

1) Define a tunable parameter for your gain block, then map this tunable parameter to an AXI4-Lite interface. Instructions on how to define a tunable parameter in a gain block can be found here:

https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-parameters.html

Once you have defined the tunable parameter, you will see a new row in the Target Interface Table for this parameter. You can map this parameter to AXI4-Lite.

2) Use a multiply block instead of a gain block, where the second input to the multiple block acts as the gain value. You can then map this input to AXI4-Lite in the Target Interface Table.

Based on your description above, it sounds like #1 will be the best option for you.

-- JT

Answer 2

[Kiran Kintali]

please review this example

Getting Started with Targeting Xilinx Zynq Platform

https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-xilinx-zynq-platform.html

[Anoop R]

Thanks a lot for your answer.

the above exmple shows how i can connect and run my board to matlab and control all the blocks in subsystem (on PL part of the board). But i dont want matlab to iteract with my board.

Once my subsystem is done i generate a IP and import this IP into vivado then i have my own software program to control ARM core. But from Vivado, using this IP from Matlab generated, I want to control blocks inside subsystem. I tried write to AXI Lite but it didnot change anything. Please look at the attached figure.

Thank you