Code generation option in HDL coder for high clock frequency

Hi,

I am working with simulink model whose code is generated by HDL coder. My design has a number of filter stages. The code generated for some filter stages performed as desired in FPGA .But when the design moves to higher clock frequencies HDL coder generated code fails to perform satisfactorily. Please inform me if there is any option to be activated in HDL coder for optimized clock generation in higher frequencies.

Krishnakumar

[Tim McBrayer]

You're going to need to be rather more specific than "fails to perform satisfactorily"; you have provided no information about the issues you are having or how the results are not reaching your expectations. You need to ask a more precise question.

Answer 1

[Kiran Kintali]

Use critical path estimation feature to estimate the critical path in your model. This workflow in HDL Coder does not involve synthesis.

https://www.mathworks.com/help///hdlcoder/ug/find-estimated-critical-paths-without-synthesis-tools.html

To get more accurate timing picture with routing delays use Back Annotation feature after synthesis step in workflow advisor.

https://www.mathworks.com/help/hdlcoder/ug/hdl-workflow-advisor-tasks.html?searchHighlight=back%20annotation&s_tid=srchtitle