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sample time mismatch

조회 수: 63 (최근 30일)
Andreas
Andreas 2011년 7월 12일
댓글: AMAL NN 2021년 4월 28일
after implementing a signal builder instead of single Steps, I get the following message:
"Incoming buses to block 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Switch' have a sample time mismatch. The signal at input port 1 of 'Thermoschock_aktuell/Rohr/Bus Creator' is of sample time [0, 0], while its corresponding signal at input port 1 of 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Bus Creator' is of sample time [0, 1]. This error message is related to a hidden SubSystem block."
This will happen with some multiport-switches in 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Switch'. I've currently no idea, why it works with steps, but not with signal builders.

채택된 답변

Andreas
Andreas 2011년 7월 14일
Thanks for the hint. Now it works, after changing sample time of the signal builder block to [0,1] (fixed in minor step).

추가 답변 (3개)

Arnaud Miege
Arnaud Miege 2011년 7월 12일
One of your busses has a continuous sample time, while the other one a discrete sample time of 1s. Use a rate transition block to convert the continuous one to a discrete one with a sample time of of 1s.
HTH,
Arnaud
  댓글 수: 1
AMAL NN
AMAL NN 2021년 4월 28일
Thank you
It works ...

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Guy Rouleau
Guy Rouleau 2011년 7월 13일
In the Signal builder, go to the file menu, there is an option to set the sample time. Change it from 0 to 1.
I recommend enabling sample time colors to better understand this sort of issues. This is done form the Format menu of the model.

Andreas
Andreas 2011년 7월 12일
Is there any possibilty to debug the system, so that rate transition is not necessary (currently I cannot find the one with "continuous time")?
Rate transition works, thanks so far :)

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