HDL Coder is intended to generate bit- and cycle-accurate, target-independent VHDL and Verilog from MATLAB and Simulink designs. The generated HDL code synthesizes very well (in terms of area and speed) in all major FPGA synthesis tools, including Xilinx ISE and Xilinx Vivado. Why don't you generate HDL code for your design with HDL Coder? Then, using your favorite Xilinx tool, you can see if the results meet your requirements.
If you have a requirement that says you must use Xilinx core blocks, you will probably need to use Xilinx System Generator blocks within Simulink. SysGen is a non-free Xilinx tool that provides a custom Blockset that maps directly to Xilinx core primitives. HDL Coder can generate code for hybrid designs, controlling and invoking SysGen on the relevant parts of the model. This can be a more tedious style of designing, as you have to treat Simulink as a schematic entry tool on the SysGen portion. This leads you to design at a lower level, focusing on the implementation, as opposed to concentrating on the algorithmic design and letting the implementation be handled by the tool chain.
