Is HDL Coder able to do falling clock edge trigger?

Looking at DDR mode, don't know if HDL Coder is capable of handling such.

Please comment, thanks,

Answer 1

[Tim McBrayer]

HDL Coder cannot generate DDR code. It is planned for R2014a to support specifying either the positive or negative clock edge to use, but even then only one edge may be used at once. This single-edge limitation is due to the simple fact that Simulink semantics to not support DDR-style semantics.