Model Configuration Parameters for Texas Instruments C2000 Processors

To configure hardware parameters for Texas Instruments^® C2000™ processors:

1. In the Simulink^® Editor, select Modeling > Model Settings.

2. In the Configuration Parameter dialog box, click Hardware Implementation.

   

3. Set the Hardware board parameter to your C2000 processors.

4. The parameter values under Hardware board settings are automatically populated to their default values.

   You can optionally adjust these parameters for your particular use case.

   

   Note

   When selecting the processing unit, choose the central processing unit (CPU) or control law accelerator (CLA) or CortexM4 onto which to deploy the model block in the model. The default values varies based on the processor selected.

5. Click Apply.

Note

In the Hardware board drop-down list, some processors have multiple options. Select the generic option for controlCARDs and custom boards, and select the LaunchPad option for LaunchPads. For example, select TI Delfino F2837xS as the generic option, and select TI Delfino F28377S Launchpad as the LaunchPad option. Based on your selection, the default values for clock settings, pin selection, and memory mapping change.

Hardware Board Settings

Parameter	Description	Default Value
Processing Unit	Processor or CLA for model block in the MCU model.	None

Task Profiling in Simulation

Parameter	Description	Default Value
Show in SDI (SoC Blockset)	Show the task execution data collected in simulation in the Simulation Data Inspector application.	on
Save to file (SoC Blockset)	Save the task execution data to a file.	on
Overwrite file (SoC Blockset)	Overwrite the last task execution data file.	off

Task Profiling on Processor

Parameter	Description	Default Value
Show in SDI (SoC Blockset)	Show the task execution data collected on hardware in the Simulation Data Inspector application.	off
Save to file (SoC Blockset)	Save the task execution data to a file.	off
Overwrite file (SoC Blockset)	Overwrite the last task execution data file.	off
Instrumentation (SoC Blockset)	Choose to perform code instrumentation or Kernel instrumentation.	Code
Profiling duration (SoC Blockset)	Choose whether to perform Kernel profiling for an unlimited or limited time duration.	Unlimited

Simulation Settings

Parameter	Description	Default Value
Set random number generator seed (SoC Blockset)	Set the random number generator seed.	off
Seed Value (SoC Blockset)	Specify the seed value for the simulation of task duration deviation.	default
Cache input data at task start (SoC Blockset)	Cache the input data at the start of a task.	off

Hardware Board Settings

For each hardware board you select, you can configure the board parameters according to your requirements.

Scheduler Options

Parameter	Description	Default Value
Base rate trigger	Set the static priority of the base rate task in the operating system.	Timer 0

Build Options

Parameter	Description	Default Value
Build action	Define how Embedded Coder® responds when you build your model.	Build, load, and run
Disable parallel build	Select to compile the generated code and driver source codes in parallel order for faster build and deployment speed.	off
Device name	Select your device from the selected processor family.
Enable TMU	Enables support for Trigonometric Math Unit (TMU).	enabled
Boot From Flash (stand alone execution)	Specify if the application loads to the flash memory.	enabled
Use custom linker command file	Indicates that the custom linker command file must be used during the build action.	off
Linker command file	The path to the memory description file required during linking.
CCS hardware configuration file	The Code Composer Studio™ file required for downloading the application on the hardware.
Enable DMA to access ePWM Registers instead of CLA	Select to access ePWM Registers
Enable DMA to peripheral frame 1 (ePWM, HRPWM, eCAP, eQEP, DAC,CMPSS, and SDFM) instead of CLA	Select to enable the DMA to access peripheral frame 1
Enable DMA to peripheral frame 2 (SPI and McBSP) instead of CLA	Select to enable the DMA to access peripheral frame 2
Enable FastRTS	Enables use of optimized floating point math functions from C28x FPU fastRTS library	enabled
Remap ePWMs for DMA access (Requires silicon revision A and above)	Select to remap ePWMs registers for DMA access
Configure CLA program and data memory	Enable this option to configure LSRAM memory for CLA program or data.	Disabled
Maximum LSRAM size for CLA program (in KW)	Select the maximum LSRAM size that is available for CLA program in KiloWords.
Maximum LSRAM size for CLA data (in KW)	Select the maximum LSRAM size that is available allowed for CLA data in KiloWords.
Available LSRAM size for CPU (in KW)	Displays the remaining available LSRAM size for CPU in KiloWords.
Use data type replacement to override precision of ‘double’ in generated code	Enable Use data type replacement to override precision of ‘double’ in generated code parameter to override precision of ‘double’ in generated code.	on
Number of bits for double	Select the number of bits for double.	32
Analyze double data type usage	Generates html report with the list of double datatype usages in model.

Clocking

Parameter	Description	Default Value
Desired CPU Clock in MHz	Specify the desired CPU clock frequency (CLKIN).
Use internal oscillator	Use the internal zero pin oscillator on the CPU.	enabled
Oscillator clock (OSCCLK) frequency in MHz	Oscillator frequency used in the processor.
Auto set PLL based on OSCCLK and CPU clock	PLL values in PLLCR, DIVSEL, and Achievable SYSCLKOUT in MHz are automatically calculated based on the CPU clock entered on the board.
PLL control register (PLLCR)	If you select Auto set PLL based on OSCCLK and CPU clock, the auto-calculated control register value matches the specified CPU clock value, based on the oscillator clock frequency.
PLL output divider (ODIV)	Calculates SYSCLKOUT = ((OSCCLK×SYSPLLMULT)/ODIV)/SYSDIVSEL.
Clock divider (DIVSEL)	If you select Auto set PLL based on OSCCLK and CPU clock, the auto-calculated control register value matches the specified CPU clock value, based on the oscillator clock frequency.
Achievable SYSCLKOUT in MHz = (OSCCLK×PLLCR)/DIVSEL	The auto-calculated feedback value that matches the Desired C28x CPU clock in MHz value, based on the values of OSCCLK, PLLCR, and DIVSEL.
Set the 'Achievable SYSCLKOUT in MHz = (OSCCLK*SYSPLLMULT)/SYSDIVSEL' value calculated in CPU1	Available only for CPU2 of dual C28x core processors. Value of this parameter must be same as the value of the parameter Achievable SYSCLKOUT in MHz = (OSCCLK*PLLCR)/DIVSEL (auto calculated).
Select the 'Low-Speed Peripheral Clock Prescaler (LSPCLK)' option used in CPU1	Available only for CPU2 of dual C28x core processors. Value of this parameter must be same as the value of the parameter Low-Speed Peripheral Clock Prescaler (LSPCLK) specified in CPU1.
Low-Speed Peripheral Clock Prescaler (LSPCLK)	Prescaler value used to calculate LSPCLK based on SYSCLKOUT.
Low-Speed Peripheral Clock (LSPCLK) in MHz	The LSPCLK value calculated using the SYSCLKOUT and LSPCLK Prescaler values.
High-Speed Peripheral Clock Prescaler (HSPCLK)	Prescaler value used to calculate HSPCLK based on SYSCLKOUT.
High-Speed Peripheral Clock (HSPCLK) in MHz	The HSPCLK value calculated using the SYSCLKOUT and HSPCLK Prescaler values.
Multiplication factor for PLL#CLK (PLL#MULT)	The multiplication factor value of PLL clock.	12
PLL clock in MHz (PLLCLK) = OSCCLK*PLLCR	The value is calculated based on Multiplication factor for PLL#CLK (PLL#MULT) and OSCCLK frequency.	120
Analog Subsystem Clock Prescaler (ASYSCLK)	Prescaler value used to calculate ASYSCLK based on SYSCLKOUT.
Analog Subsystem Clock (ASYSCLK) in MHz	The ASYSCLK value calculated using the SYSCLKOUT and ASYSCLK Prescaler values.
Connectivity Manager (ARM Cortex-M) clock source	Select the clock source for ARM Cortex-M core.	System PLL
Connectivity Manager (ARM Cortex-M) clock divider	Select the divider for the ARM Cortex-M core clock.	4
Connectivity Manager (ARM Cortex-M) clock in MHz	The calculated value of the clock frequency (in MHz) supplied to ARM Cortex-M core.	100

ADC_x

Parameter	Description	Default Value
Select the CPU core which controls ADC_x module	The CPU core that controls the ADC module.	Auto
ADC clock prescaler (ADCCLK)	The ADCCLK divider for the c2802x, c2803x, c2806x, F28M3x, F2807x, or F2837x processor.	SYSCLKOUT/5.0
ADC clock frequency in MHz	The clock frequency for ADC, which is auto generated based on the value you select in ADC clock prescaler (ADCCLK).	40
ADC overlap of sample and conversion (ADC#NONOVERLAP)	Enable or disable overlap of sample and conversion.
ADC clock prescaler (ADCLKPS)	The HSPCLK is divided by ADCLKPS (a 4-bit value) as the first step in deriving the core clock speed of the ADC.	3
ADC Core clock prescaler (CPS)	After dividing the HSPCLK speed by the ADC clock prescaler (ADCLKPS) value, divides the result by 2.	1
ADC Module clock (ADCCLK = HSPCLK/ADCLKPS×2)/(CPS+1)) in MHz	The ADC module clock, which indicates the ADC operating clock speed.
Acquisition window prescaler (ACQ_PS)	Determine the width of the sampling or acquisition period. A higher value indicates a wider sampling period.	4
Acquisition window size ((ACQ_PS+1)/ADCCLK) in micro seconds/channel	Determine the duration for which the sampling switch is closed.
Offset	Specify the offset value.
Use external reference 2.048V	Allows using a 2.048 V external voltage reference.
Use external reference	Allows using an external voltage reference.
Continuous mode	When the ADC generates an end of conversion (EOC) signal, an ADCINT# interrupt is generated. The interrupt indicates whether the previous interrupt flag has been acknowledged.
ADC offset correction (OFFSET_TRIM: –256 to 255)	The 280x ADC supports offset correction using a 9-bit value that it adds or subtracts before the results are available in the ADC result registers.	0
VREFHI, VREFLO	When you disable the Use external reference 2.048V or External reference option, the ADC logic uses a fixed 0–3.3 V input range, and VREFHI and VREFLO are disabled. To interpret the ADC input as a ratiometric signal, select the External reference option. Then, set values for the high-voltage reference (VREFHI) and the low voltage reference (VREFLO).
INT pulse control	Set the time when the ADC sets ADCINTFLG ADCINTx relative to the SOC and EOC pulses.
SOC high priority	Enable SOC high priority mode.	All in round robin mode
XINT2SOC external pin	The pin to which the ADC sends the XINT2SOC pulse.
ADCEXTSOC external pin	The GPIO pin from which ADC receives the ADCEXTSOC pulse.	GPIO#
ADCEXTSOC Input X-BAR	Indicates the input of X-BAR for ADC external SOC.	Input#

COMP

Parameter	Description	Default Value
Comparator x (COMPx) pin assignment	Assign COMP pin to a GPIO pin.

DAC

Parameter	Description	Default Value
DACx reference voltage	Select the reference voltage for the DAC channel A, B, or C.	ADC reference voltage (VREFHIA/VREFHIB)
DACx synchronization signal	Select the synchronization signal to load the value from the writable shadow register into the active register.	SYSCLK

CAN_x

Parameter	Description	Default Value
CAN module clock frequency (= SYSCLKOUT) in MHz	The clock for the enhanced CAN module.	200
CAN module clock frequency (=SYSCLKOUT/2) in MHz	The clock for the enhanced CAN module.
Baud rate prescaler (BRP: 2 to 256)/Baud rate prescaler (BRP: 1 to 1024)	Scale the bit rate using this value.	20
Time segment 1 (TSEG1)	Set the value of time segment 1. This value, with TSEG2 and Baud rate prescaler, determines the length of a bit on the CAN bus.
Time segment 2 (TSEG2)	Set the value of time segment 2. This value, with TSEG1 and Baud rate prescaler, determines the length of a bit on the CAN bus.
Baud rate (CAN Module Clock/BRP/(TSEG1 + TSEG2 +1)) in bits/sec	CAN module communication speed represented in bits/second.
SBG	Set the message resynchronization triggering.
SJW	Set the synchronization jump width, which determines how many units of TQ a bit can be shortened or lengthened by when resynchronizing.
SAM	Number of samples used by the CAN module to determine the CAN bus level.
Enhanced CAN Mode	Enable time stamping and usage of Mailbox Numbers 16 through 31 in the C2000 CAN blocks.
Self test mode	If you set this parameter to True, the CAN module goes to loopback mode. The loopback mode sends a dummy acknowledge message back.	False
Pin assignment (Tx)	Assign the CAN transmit pin to use with the CAN_B module.
Pin assignment (Rx)	Assign the CAN receive pin to use with the CAN_B module.

eCAP

Parameter	Description	Default Value
ECAPx capture pin assignment	Indicates the GPIO pin used for eCAP in capture mode.	GPIO#
ECAPx Input X-BAR	Select input X-BAR for ECAP	INPUT#
ECAPx APWM pin assignment	The GPIO pin to which output of the eCAP in APWM mode is sent.	GPIO#
Output X-BAR	Indicates which Output X-BAR is used for the selected ECAP# APWM pin assignment parameter.	#
eCAPxSYNCIN source selection	Indicates the SYNC source select register for the ePWM SYNCOUT, eCAP SYNCOUT, INPUTXBAR and EtherCATSYNC.	The default eCAPxSYNCIN source selection value varies based on the processor selected.

ePWM

Parameter	Description	Default Value
EPWM clock divider (EPWMCLKDIV)	Select the ePWM clock divider.	SYSCLKOUT/1
Select the 'EPWM clock divider (EPWMCLKDIV)' option used for CPU1	Available only for CPU2 of dual C28x core processors. Its value must be the same as the value of the parameter EPWM clock divider (EPWMCLKDIV) selected in CPU1.
TZx Input X-BAR	Indicates the trip-zone input X-BAR.	INPUT#
TZx pin assignment	Indicates the GPIO pin to the trip-zone input x (TZx).	None
TRIP# MUX select	Select the TRIP Multiplexer(MUX).	Disable all
TRIP# MUX (MUX 0->31)	Indicates the inputs selected for each MUX so far.	XXXXXXXXXXX
Select MUX input	Select the input to the Multiplexer selected in TRIP# MUX select.	X:Disable
Reset TRIP# MUX	Option to reset the MUX inputs selected.
Invert TRIP output	Inverts the TRIP output signal.	off
SYNCI Input X-BAR	Indicates the SYNCI input X-BAR.	INPUT#
SYNCI pin assignment	Indicates the GPIO pin used for the ePWM external sync pulse input (SYNCI).	None
SYNCO pin assignment	Assign the ePWM external sync pulse output (SYNCO) to a GPIO pin.
EXTSYNCOUT source selection	Select the external SYNCOUT source for ePWM	Default value varies based on the processor selected
ePWMxSYNCIN source selection	Select the EPWMxSYNCIN Source Select Register (synchronization input pulse) for the ePWM	Default value varies based on the processor selected
PWM#x pin assignment	Assign the GPIO pin to the PWM#x module.	GPIO#
GPTRIP#SEL pin assignment(GPIO0~63)	Assign the ePWM trip-zone input to a GPIO pin.
PWM1SYNCI/ GPTRIP6SEL pin assignment	Assign the ePWM sync pulse input (SYNCI) to a GPIO pin.
DCxHTRIPSEL (Enter Hex value between 0 and 0x6FFF)	Assign the Digital Compare A high trip input to a GPIO pin.
DCxLTRIPSEL (Enter Hex value between 0 and 0x6FFF)	Assign the Digital Compare A low trip input to a GPIO pin.

I2C

Parameter	Description	Default Value
Mode	Configure the I2C module as controller or peripheral.
Addressing format	In peripheral mode, determines the addressing format of the I2C controller and sets the I2C module to the same mode.
Own address register	In peripheral mode, enter the 7-bit (0–127) or 10-bit (0–1023) address that the I2C module uses.
Bit count	In peripheral mode, sets the number of bits in each data byte the I2C module transmits and receives.
Module clock prescaler (IPSC: 0 to 255)	In controller mode, enter a value in the range 0–255, inclusive, to configure the model clock frequency.
I2C Module clock frequency (SYSCLKOUT / (IPSC+1)) in Hz	Display the frequency the I2C module uses internally. To set this value, change the Module clock prescaler.
I2C controller clock frequency (Module Clock Freq/(ICCL+ICCH+10)) in Hz	Display the controller clock frequency.
controller clock Low-time divider (ICCL: 1 to 65535)	In controller mode, determines the duration of the low state of the SCL on the I2C bus.
controller clock High-time divider (ICCH: 1 to 65535)	In controller mode, determines the duration of the high state of the SCL on the I2C bus.
Enable loopback	In controller mode, enables or disables digital loopback mode.
SDA pin assignment	Select a GPIO pin as an I2C data bidirectional port.
SCL pin assignment	Select a GPIO pin as an I2C clock bidirectional port.
Enable Tx interrupt	This parameter corresponds to bit 5 (TXFFIENA) of the I2C Transmit FIFO Register (I2CFFTX).
Tx FIFO interrupt level	This parameter corresponds to bits 4–0 (TXFFIL4-0) of the I2C transmit FIFO register (I2CFFTX).
Enable Rx interrupt	This parameter corresponds to bit 5 (RXFFIENA) of the I2C receive FIFO register (I2CFFRX).
Rx FIFO interrupt level	This parameter corresponds to bit 4–0 (RXFFIL4-0) of the I2C receive FIFO register (I2CFFRX).
Enable system interrupt	Select this parameter to configure the five basic I2C interrupt request parameters in the interrupt enable register (I2CIER).
Enable AAS interrupt	Enable the addressed-as-peripheral interrupt bit.
Enable SCD interrupt	Enable the stop condition detected interrupt bit.
Enable ARDY interrupt	Enable the register-access-ready interrupt bit.
Enable NACK interrupt	Enable the no acknowledgment interrupt bit.
Enable AL interrupt	Enable the arbitration-lost interrupt bit.

SCI_x

Parameter	Description	Default Value
Enable loopback	Enable the loopback function for self-test and diagnostics.
Suspension mode	The type of suspension to use while debugging your program with Code Composer Studio.
Number of stop bits	Specify the number of stop bits transmitted.
Parity mode	The type of parity to use.
Character length bits	Length in bits of each transmitted or received character.	8
Desired baud rate in bits/sec	Specify the desired baud rate.
Baud rate prescaler (BRR = (SCIHBAUD << 8) | SCILBAUD))	Scale the SCI baud rate using this value.
Closest achievable baud rate (LSPCLK/(BRR+1)/8) in bits/sec	The closest achievable baud rate, calculated based on LSPCLK and BRR.
Communication mode	Select the mode for transmitting and receiving data.
Post transmit FIFO interrupt when data is transmitted	Posts interrupt when available data in transmit FIFO is less than or equal to interrupt level.	off
Transmit FIFO interrupt level	Level for triggering SCI transmit interrupt.	1
Post receive FIFO interrupt when data is received	Posts interrupt when available data in receive FIFO is greater than or equal to interrupt level.	off
Receive FIFO interrupt level	Level for triggering SCI receive interrupt.	1
Data byte order	Select an option to match the endianness of the data being moved.
Pin assignment (Tx)	Assign the SCI transmit pin to use with the SCI module.
Pin assignment (Rx)	Assign the SCI receive pin to use with the SCI module.

SPI_x

Parameter	Description	Default Value
Mode	Set to controller or peripheral.
Desired baud rate in bits/sec	Specify the desired baud rate.
Baud rate factor (SPIBRR: between 3 and 127)	The value used to calculate the baud rate.
Closest achievable baud rate (LSPCLK/(SPIBRR+1)) in bits/sec	The closest achievable baud rate, calculated based on LSPCLK and SPIBRR.
Suspension mode	The type of suspension to use while debugging your program with Code Composer Studio.
Enable loopback	Enable the loopback function for self-test and diagnostics.	off
Enable 3-wire mode	Enables SPI communication over three pins instead of the normal four pins.	off
Enable Tx interrupt	Enable SPI transmit interrupt operation.	off
FIFO interrupt level (Tx)	Set level for transmit FIFO interrupt.	0
Enable Rx interrupt	Enable SPI receive interrupt operation.	off
Enable high speed mode	Enable high speed SPI mode for supported pins.
FIFO interrupt level (Rx)	Set level for receive FIFO interrupt.
FIFO transmit delay	FIFO transmit delay (in processor clock cycles) to pause between data transmissions.
Peripheral in controller out pin assignment	Assign the SPI (SIMO) to a GPIO pin.
Peripheral out controller in pin assignment	Assign the SPI value (SOMI) to a GPIO pin.
CLK pin assignment	Assign the CLK pin to a GPIO pin.
STE pin assignment	Assign the SPI value (STE) to a GPIO pin.

eQEP

Parameter	Description	Default Value
EQEP#x pin assignment	Assign eQEP pin to a GPIO pin.

Watchdog

Parameter	Description	Default Value
Enable watchdog	Enable the watchdog timer module.
Counter clock	Set the watchdog timer period relative to OSCCLK/512.
Timer period ((1/Counter clock)×256) in seconds	Display the timer period in seconds. This value automatically updates when you change the Counter clock parameter.
Time out event	Configure the watchdog to reset the processor or generate an interrupt when the software fails to reset the watchdog counter.

GPIO

Parameter	Description	Default Value
GPIO#	Use the GPIO pins for digital input or output by connecting to one of the three peripheral I/O ports.

DMA_ch#

Parameter	Description	Default Value
Enable DMA channel	Enable to edit the configuration of a specific DMA channel.
Data size	Select the size of the data bit transfer.
Interrupt source	Select the peripheral interrupt that triggers a DMA burst for the specified channel.
SRC wrap	Specify the number of bursts before returning the current source address pointer to the Source Begin Address value.
DST wrap	Specify the number of bursts before returning the current destination address pointer to the Destination Begin Address value.
SRC Begin address	Set the starting address for the current source address pointer.
DST Begin address	Set the starting address for the current destination address pointer.
Burst	Specify the number of 16-bit words in a burst, from 1 to 32.
Transfer	Specify the number of bursts in a transfer, from 1 to 65536.
SRC Burst step	Increment or decrement the current address pointer by this number of 16-bit words before the next burst.
DST Burst step	Increment or decrement the current address pointer by this number of 16-bit words before the next burst.
SRC Transfer step	Increment or decrement the current address pointer by this number of 16-bit words before the next transfer.
DST Transfer step	Increment or decrement the current address pointer by this number of 16-bit words before the next transfer.
SRC Wrap step	Increment or decrement the SRC_BEG_ADDR address pointer by this number of 16-bit words when a wrap event occurs.
DST Wrap step	Increment or decrement the DST_BEG_ADDR address pointer by this number of 16-bit words when a wrap event occurs.
Generate interrupt	Enable this parameter to have the DMA channel send an interrupt to the CPU through the Peripheral Interrupt Expansion (PIE) at the beginning or end of a data transfer.
Enable one shot mode	Enable this parameter to have the DMA channel complete an entire transfer in response to an interrupt event trigger.
Sync enable	Enable this parameter to reset the DMA wrap counter when the Interrupt source is set to SEQ1INT and sends the ADCSYNC signal to the DMA wrap counter.
Enable continuous mode	Select this parameter to leave the DMA channel enabled upon completing a transfer. The channel waits for the next interrupt event trigger.
Enable DST sync mode	Enabling this parameter resets the destination wrap counter (DST_WRAP_COUNT) when Sync enable is enabled and the DMA module receives the SEQ1INT interrupt/ADCSYNC signal.
Set channel 1 to highest priority	Enable this option when DMA channel 1 is configured to handle high-bandwidth data, such as ADC data, and the other DMA channels are configured to handle lower-priority data.
Enable overflow interrupt	Enable this parameter to have the DMA channel send an interrupt to the CPU through the PIE if the DMA module receives a peripheral interrupt while a previous interrupt from the same peripheral is waiting to be serviced.

EMIF#

Parameter	Description	Default Value
EMIF clock divider (EMIF1CLKDIV)	Clock divider for clock frequency generation.	SYSCLKOUT/2
Enable CS0 for Synchronous memory	Chip select (CS0) to interface with the SDRAM.	off
Enable CS# for Asynchronous memory	Chip select (CS2/CS3/CS4) to interface with the asynchronous RAM.	off
SDRAM Column address bits	Value of the column address bits or the required page size of the connected SDRAM.	8
Number of internal SDRAM banks	Number of memory banks inside the connected SDRAM.	3
SDRAM data bus width in bits	Data bus width of the connected SDRAM.	16
Refresh to active command delay cycles (T_RFC)	Minimum number of EM#CLK cycles from the refresh or load mode command to the refresh or activate command in the connected SDRAM.	3
Row precharge to Active command delay cycles (T_RP)	Minimum number of EM#CLK cycles required from the row precharge command to the activate or refresh command in the connected SDRAM.	1
Active to read or write command delay cycles (T_RCD)	Minimum number of EM#CLK cycles from the activate command to the read or write command in the connected SDRAM.	2
Last write to row precharge command delay cycles (T_WR)	Minimum number of EM#CLK cycles from the last write transfer or last data in command to the row precharge command in the connected SDRAM.	1
Active to precharge command delay cycles (T_RAS)	Minimum number of EM#CLK cycles from the activate command to the row precharge command in the connected SDRAM.	4
Active to active command delay cycles (T_RC)	Minimum number of EM#CLK cycles from an activate command to the next activate command in the same bank in the connected SDRAM.	6
Active one bank to active another bank command delay cycles (T_RRD)	Minimum number of EM#CLK cycles from an activate command in one bank to an activate command in a different bank in the connected SDRAM.	1
Self-refresh exit to other command delay cycles (T_XSR)	Minimum number of EM#CLK cycles from the self refresh exit command to any other command in the connected SDRAM.	7
SDRAM refresh period (tRefreshPeriod) in ms	Defines the rate at which the connected SDRAM refreshes.	64
SDRAM CAS Latency	CAS latency required to access the connected SDRAM.	3
Asynchronous mode	Asynchronous mode for the connected asynchronous memory.	Normal
Asynchronous data bus width in bits	Data bus width of the connected asynchronous memory.	16
Read strobe setup cycles (R_SETUP)	Number of EM#CLK cycles from the EMIF chip select to the pin enable for asynchronous memory assert.	15
Read strobe duration cycles (R_STROBE)	Number of EM#CLK cycles during which the pin enable for the asynchronous memory is held active.	64
Read strobe hold cycles (R_HOLD)	Number of EM#CLK cycles during which the EMIF chip select is held active after pin enable for the asynchronous memory is deasserted.	7
Write strobe setup cycles (W_SETUP)	Number of EM#CLK cycles from the EMIF chip select to the write enable for the asynchronous memory assert.	15
Write strobe duration cycles (W_STROBE)	Number of EM#CLK cycles during which the write enable for the asynchronous memory is held active.	63
Write strobe hold cycles (W_HOLD)	Number of EM#CLK cycles during which the EMIF chip select is held active after write enable for the asynchronous memory is deasserted.	7
Turn around cycles (TA)	Number of EM#CLK cycles between the end of one asynchronous memory access and the start of another asynchronous memory access.	3
Enable extended wait mode	Enable the extended wait option for the asynchronous memory.	off
Maximum extended wait cycles for Asynchronous memory (MAX_EXT_WAIT) [0–255]	EMIF waits for (MAX_EXT_WAIT+1) * 16 clock cycles before the asynchronous cycle is terminated.	128
Pin polarity of extended wait	Make EMIF wait if the pin is low or high.	High
Enable wait rise interrupt	Get an interrupt based on the detection of a rising edge on the EM#WAIT pin.	off
Enable timeout interrupt	Get an interrupt when the EM#WAIT pin does not become inactive within the number of cycles defined in Maximum extended wait cycles for Asynchronous memory (MAX_EXT_WAIT) [0–255].	off
Enable line trap interrupt	Get an interrupt when there is an invalid cache line size or illegal memory access.	off

LIN

Parameter	Description	Default Value
LIN Module clock frequency (LM_CLK = SYSCLKOUT/2) in MHz	Display the frequency of the LIN module clock in MHz.
Enable loopback	Enable LIN loopback testing.
Suspension mode	Use this option to configure how the LIN state machine behaves while you debug the program using an emulator.	Free_run
Parity mode	Use this option to configure parity checking.	None
Frame length bytes	Set the number of data bytes in the response field, from 1–8 bytes.	8
Baud rate prescaler (P: 0-16777215)	To set the LIN baud manually, enter a prescaler value from 0–16777215.	15
Baud rate fractional divider (M: 0–15)	To set the LIN baud manually, enter a fractional divider value from 0–15.	4
Baud rate (FLINCLK = LM_CLK/(16×(P+1+M/16)) in bits/sec	Display the baud rate.
Communication mode	Enable or disable the LIN module from using the ID-field bits ID4 and ID5 for length control.	ID4 and ID5 not used for length control
Data byte order	Set the endianness of the LIN message data bytes.	Little_Endian
Data swap width	Set the width for data swap.
Pin assignment (Tx)	Map the LINTX output to a specific GPIO pin.	GPIO9
Pin assignment (Rx)	Map the LINRX input to a specific GPIO pin.	GPIO11
LIN mode	Set the LIN module as a controller or a peripheral.	peripheral
ID filtering	Select the type of mask filtering comparison the LIN module performs.	ID peripheral task byte
ID byte	If you set ID filtering as ID byte, use this option to set the ID BYTE, also known as the “LIN mode message ID”.	0x3A
ID peripheral task byte	If you set ID filtering to ID peripheral task byte, use this option to set the ID-peripheralTask BYTE.	0x30
Checksum type	Select the checksum type.	Classic
Enable multibuffer mode	When you select this check box, the LIN node uses transmit and receive buffers instead of just one register.	Selected
Enable baud rate adapt mode	This option is displayed when you set LIN mode to peripheral.	Not selected
Inconsistent synch field error interrupt	If you enable this option, the peripheral node generates interrupts when it detects irregularities in the synch field.	Disabled
No response error interrupt	If you enable this option, the LIN module generates an interrupt if it does not receive a complete response from the controller node within a timeout period.	Disabled
Timeout after 3 wakeup signals interrupt	When enabled, the peripheralnode generates an interrupt when it sends three wakeup signals to the controller node and does not receive a header in response.	Disabled
Timeout after wakeup signal interrupt	When enabled, the peripheral node generates an interrupt when it sends a wakeup signal to the controller node and does not receive a header in response.	Disabled
Timeout interrupt	When enabled, the peripheral node generates an interrupt after 4 seconds of inactivity on the LIN bus.	Disabled
Wakeup interrupt	The LIN peripheral mode generates a wakeup interrupt based on a request or condition.	Disabled

External Interrupt

Parameter	Description	Default Value
XINT# Input X-BAR	Indicates the input X-BAR for external interrupt.	Input#
XINT# GPIO	The GPIO pin for external interrupt.	0
XINT# Polarity	Set the polarity for external interrupt.	Falling edge

External Mode

Parameter	Description	Default Value
Communication interface	Select the type of communication interface to run your model in external mode.	XCP on Serial
SCI module	Select the serial communication interface module.	SCI_A
Serial port in MATLAB preferences	Select the COM port used by the target hardware.
Host Interface	Select the interface through which the host computer communicates to target hardware for signal monitoring and parameter tuning.	Third party calibration tools
CAN module	Select the CAN module to be used with external mode	CAN_A
CAN ID Command	Enter the CAN ID Command for the CAN module.	2
CAN ID Response	Enter the CAN ID Response for the CAN module.	3
CAN vendor	Enter the CAN vendor for the CAN module.	<empty>
CAN device	Enter the device for the CAN module.	<empty>
CAN channel number	Enter the CAN channel number for the CAN module.	<empty>
Extended CAN ID	Select to use extended ID.	off
Rx mailbox number	Enter the Rx mailbox number for the CAN module.	0
Tx mailbox number	Enter the Tx mailbox number for the CAN module.	1
Verbose	Select to view the external mode execution progress and updates in the Diagnostic Viewer or in the MATLAB® command window.	off
Set logging buffer size automatically	Select to automatically set the number of bytes to preallocate for the buffer in the hardware during simulation.	on
Maximum number of contiguous samples	Specify a value for maximum number of contiguous samples parameter.	8
Use a dedicated timer to improve time stamp accuracy	Select to log data inside ISR at ISR trigger rate	off

Execution Profiling

Parameter	Description	Default Value
Number of profiling samples to collect	Enter the number of profiling samples to collect.

SD Card Logging

Parameter	Description	Default Value
Enable MAT-file logging on SD card	Enables the MAT-file logging for SD card.	off
SPI module	Select the desired interface on which the SD card is connected to hardware board.
SPI baud rate	Select the desired option for the SPI interface used by the SD card.	Maximum achievable supported by the inserted SD Card

CMPSS

Parameter	Description	Default Value
Configure CMPSS#	Configure the comparator subsystem (CMPSS).	off
Configure COMP#	Configure the COMPH or COMPL module.	off
Reload condition for RAMP reference value (RAMPLOADSEL)	Reload condition for RAMP reference value.	Immediate (RAMPMAXREFA)
Invert comparator output	Invert comparator output.	off
Enable latch clear by EPWMSYNCPER event	Enable latch clear by EPWMSYNCPER event.	off
Configure digital filter	Configure the digital filter for COMP#.	off
Sample clock prescale [0 to 1023]	Set the sample clock prescale for digital filter of COMP#.	0
Sample window size	Set the sample window size for digital filter of COMP#.	0
Threshold sample size	Set the threshold sample window size for digital filter of COMP#.	0
Comparator output type for EPWM X-BAR (CTRIP#SEL)	Select the comparator output type source for COMP#.	Asynchronous output (ASYNCH)
Comparator output type for OUTPUT X-BAR (CTRIPOUT#SEL)	Select the comparator output type source for COMP#.	Asynchronous output (ASYNCH)
DAC reference voltage	Select the DAC reference voltage for CMPSS.	Internal reference voltage (VDDA)
Reload condition for DAC value (SWLOADSEL)	Select the reload condition for DAC value.	System clock (SYSCLK)
EPWM peripheral synchronization event	Select the EPWM peripheral synchronization event.	EPWM1SYNCPER
EPWM blank window event	Select the EPWM for blanking window	EPWM1BLANK
Comparator hysteresis value	Set the amount of hysteresis on the comparator inputs.	0

SDFM#

Parameter	Description	Default Value
Configure filter#	Configure the filter channel for the SDFM module.	off
Data pin assignment (SD#_D#)	Select the data pin for the GPIO configuration.	GPIO#
Clock pin assignment (SD#_C#)	Select the clock pin for the GPIO configuration.	GPIO#
Modulator clock mode	Select the modulator clock mode.	Same as the modulator data rate (MOD_0)
Comparator filter type	Select the comparator filter type.	Sinc1
Comparator over sample ratio (COSR) [0-31]	Specify the comparator OSR value.	0
Comparator higher threshold (HLT#) [0-32767]	Specify the comparator higher threshold value to detect an over-value condition.	0
Comparator lower threshold (LLT#) [0-32767]	Specify the comparator lower threshold value to detect an under-value condition.	0
Comparator higher threshold (HLTZ) [0-32767]	Specify the comparator higher threshold value to detect over-value condition.	0
Data filter type	Select the data filter type.	Sinc1
Data over sampling ratio (DOSR) [0-255]	Specify the data OSR value.	0
Data filter FIFO depth	Specify the FIFO value for the data filter.	0
Enable data filter reset by PWM	Enable to reset the data filter by external PWM compare output.	off
ePWM module	Select the ePWM module for synchronization.	PWM#SOCA
Comparator event # (CEVT#) interrupt	Select the comparator event (CEVT#) interrupt.	Disable
Enable high level threshold crossing output (HLTZ)	Enable threshold crossing event detection.	off
Enable modulator clock failure interrupt	Enable the interrupt for modulator clock failure.	off
Enable data filter acknowledge interrupt	Enable the interrupt for new data acknowledgment.	off
Enable comparator higher threshold (HLT)	Enable to detect an over-value condition.	off
Enable comparator lower threshold (LLT)	Enable to detect an under-value condition.	off
Synchronize SD Data with PLLCLK	Select to synchronize the data input to a filter with the PLL clock.	off
Synchronize SD Clock with PLLCLK	Select to synchronize the clock input to a filter with the PLL clock.	off

PIL

Parameter	Description	Default Value
Communication interface	Select the type of communication interface to run your model.	Serial
SCI module	Select the serial communication interface module.	SCI_A
Serial port in MATLAB preferences	Select the COM port used by the target hardware.

Analog subsystem

Parameter	Description	Default Value
External references for VREFHIx	Allows using an external voltage reference.	off
VREFHIx	High voltage reference.	3.3

Overrun detection

Parameter	Description	Default Value
Enable overrun detection	Enable to notify when task overrun occurs.	off
Set/Clear/toggle GPIO	Enable to select GPIO action.	on
Digital output pin to set an overrun	Specify the GPIO number of a digital output.	34
GPIO set mode	Select the GPIO mode.	Set
Additional notification option	Select the additional option to notify when task overrun occurs.	None
PIE number	Specify the PIE number for the interrupt to trigger on overrun.	1
CPU number	Specify the CPU number for the interrupt to trigger on overrun.	1
Name of the function	Specify the name of the C function to call on overrun.	C2000_OverunFunction

INPUT X-BAR

Parameter	Description	Default Value
INPUT# pin assignment	Specify the GPIO pin for input X-BAR.	None

OUTPUT X-BAR

Parameter	Description	Default Value
OUTPUT# MUX select	Select the output multiplexer(MUX).	Disable all
Select MUX input	Select the input to the MUX selected for OUTPUT# MUX select.	X:Disable
OUTPUT# MUX (MUX 0->31)	Indicates the input signal selected for each output MUX.	XXXXXXXXXXXXXXXXXXXXXXX
Reset OUTPUT# MUX	Option to reset the MUX inputs selected.
OUTPUT# pin assignment	Select the GPIO pin for the output X-BAR MUX signals.	GPIO#
Enable OUTPUT# latch	Enables the output latch to drive the respective output X-BAR.	off
Invert OUTPUT#	Inverts the output X-BAR signal.	off

CLB X-BAR

Parameter	Description	Default Value
AUXSIG# MUX select	Select the MUX to map the signal to AUXSIG# MUX.	Disable all
Select MUX input	Select the input to the MUX selected for AUXSIG# MUX select.	X:Disable
AUXSIG# MUX (MUX 0->31)	Indicates the input signal selected for each AUXSIG MUX.	XXXXXXXXXXXXXXXXXXXXXXX
Reset AUXSIG# MUX	Option to reset the MUX inputs selected.
Invert AUXSIG#	Inverts the CLB X-BAR signal or Inverts the AUXSIG# signal.	off

CLB

Parameter	Description	Default Value
Enable CLB Tile #	Select this option to enable the CLB tile.	off
Tile # Name	Specify the tile name. This tile name will be used to generate the required function declaration and calling the function for CLB tile configuration file (clb_config.c and clb_config.h) generated using CLB tool. The tile names entered here should be an exact match with the tile name set in CLB tool to generate the file.	TILE#
IN# MUX selection	Configure the signal source type for the IN# mux. The type of signal can be global inputs, local inputs and GPREG.	Global inputs
Input	Configure the peripheral signal as input to the CLB tile.	ePWM#A
Input filtering	Configure the type of input filtering for the signal type Global inputs and Local inputs. This option will be disabled for GPREG as it is not applicable.	No filtering
Enable sync	Configure the synchronization option (SYNC) for the Global inputs and Local inputs IN# mux selection only. This option is not applicable for GPREG type and will be disabled for the same.	off
Route OUT# signal to	Option to enable routing the CLB output signal to the peripheral instead of the default peripheral signal. Each CLB output signal passes through an external multiplexer that intersects a specific peripheral signal. If the options in this parameter is enabled it will route the CLB output for the specific peripheral instead of the original peripheral signal.
CLB configuration header file (clb_config.h)	Provide the paths for the CLB configuration header file clb_config.h generated using CLB tool. This file holds the required function declarations and headers used to configure the CLB tile.	clb_config.h
CLB configuration source file (clb_config.c)	Provide the paths for the CLB configuration source file clb_config.c generated using CLB tool. This file holds the required function definitions used to configure the CLB tile.	clb_config.c
Browse	Click this button to browse the path for the file selection.
Edit	Click this button to open the existing file for editing in MATLAB editor.

HRCAP Model Configuration

Parameter	Description	Default Value
HRCAP pin assignment	Select the GPIO pin for the respective HRCAP module.	GPIO#

MCAN

Parameter	Description	Default Value
Protocol mode	Select the CAN type. Classic CAN or CAN-FD.	CAN-FD
MCAN module clock frequency (=connectivity manager (ARM Cortex-M) clock)in MHz	Displays the MCAN module clock frequency in MHz.	100
MCAN bit clock frequency (MCAN module clock freq/4) in MHz	Displays the MCAN bit clock frequency in MHz.	25
Nominal bit rate prescaler (NBRP: 1 to 512)	Nominal bit rate prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta.	1
Nominal time segment 1 (NTSEG1: 2 to 256)	Nominal time segment before sample point.	22
Nominal time segment 2 (NTSEG2: 2 to 128)	Nominal time segment after sample point.	2
Closest achievable nominal baud rate (MCAN bit clock/NBRP/(NTSEG1+NTSEG2)) in bits/sec	Closest achievable nominal MCAN baud rate in bits/sec.	1000000
Nominal re-synchronization jump width (NSJW: 1 to 128)	Nominal Resynchronization Jump Width (NSJW).	1
Enable bit rate switching	Enables bit rate switching between nominal bit rate and data bit rate.	off
Data bit rate prescaler (DBRP: 1 to 32)	Data Bit Rate Prescaler (DBRP). The value by which the oscillator frequency is divided for generating the bit time quanta.	1
Data time segment 1 (DTSEG1: 1 to 32)	Data time segment before sample point (DTSEG1).	22
Data time segment 2 (DTSEG2: 1 to 16)	Data time segment after sample point (DTSEG2).	2
Data baud rate (MCAN bit clock/DBRP/(DTSEG1+DTSEG2)) in bits/sec	Closest achievable MCAN data baud rate calculated based on data parameters and given formula.	1000000
Data re-synchronization jump width (DSJW: 1 to 16))	Data resynchronization jump width (DSJW).	1
Mode	Select the operating mode for MCAN.	Normal
Pin assignment(Tx)	Select a GPIO pin for the MCAN data transmission.	GPIO 31
Pin assignment(Rx)	Select a GPIO pin for the MCAN data reception.	GPIO 30
Transmission mode	Select the mode of transmission.	FIFO
Enable blocking mode for Rx FIFO 0	Enable blocking mode for FIFO 0 data reception.	off
Enable blocking mode for Rx FIFO 1	Enable blocking mode for FIFO 1 data reception.	off
Update global filter configuration	Enable this parameter to update standard and extended filter IDs.	off
Reject remote frames standard	Rejects all remote frames with 11-bit standard IDs when enabled else the remote frames will be filtered as per the settings from Update standard filter elements.	off
Reject remote frames extended	Rejects all remote frames with 29-bit extended IDs when enabled else the remote frames will be filtered as per the settings from Update extended filter elements.	off
Non-matching frames extended	Defines how received messages with 11-bit standard IDs that do not match any element from Update standard filter elements are treated.	Accept in Rx FIFO 0
Non-matching frames standard	Defines how received messages with 29-bit extended IDs that do not match any element from Update extended filter elements are treated.	Accept in Rx FIFO 0
Update standard filter elements	Enable this parameter to update the standard 11bit ID filter elements parameters.	off
Select standard filter	Select the standard message ID filter elements.	0
Filter # configuration	Select the standard filter element configuration.	Disable filter element
Filter # type (filter type will be ignored if filter configuration is stored into Rx buffer)	Select the standard filter type.	Classic ID and mask filter (ID1 = filter, ID2 = mask)
Filter # ID1	Specify the standard Filter ID 1.	0
Filter # ID2	Specify the standard Filter ID 2.	0
Update extended filter elements	Enable to update the extended filter elements.	off
Select extended filter	Select the extended message ID filter elements.	0
Filter # configuration	Select extended filter element configuration.	Disable filter element
Filter # type (filter type will be ignored if filter configuration is stored into Rx buffer)	Select the extended filter type.	Classic ID and mask filter (ID1 = filter, ID2 = mask)
Filter # ID1	Specify the first ID of extended ID filter element.	0
Filter # ID2	Specify the second ID of extended ID filter element.	0
Display configured extended and standard filters elements in command window	Click on Display configured extended and standard filters elements in command window button to view the configured standard and extended filter elements in MATLAB command window.
Reset standard filters configurations	Click Reset standard filters configurations to reset the configured standard filter configurations.
Reset extended filters configurations	Click Reset extended filters configurations to reset the configured extended filter configurations.
Configure memory	Select to configure the memory and its parameters.	off
Maximum element size in TX FIFO (in bytes)	Select the maximum data size of CAN FD message in transmit FIFO.	64
Maximum element size in RX FIFO 0 (in bytes)	Select the maximum data size of CAN FD message in receive FIFO 0.	64
Maximum element size in RX FIFO 1 (in bytes)	Select the maximum data size of CAN FD message in receive FIFO 1.	64
Maximum element size in RX buffer (in bytes)	Select the maximum data size of CAN FD message in receive buffer.	64
Number of elements in TX FIFO Queue	Select the number of elements (data + header CAN FD message) in transmit FIFO/Queue.	32
Number of elements in RX FIFO 0	Select the number of elements (data + header CAN FD message) in receive FIFO 0.	Auto allocate
Number of elements in RX FIFO 1	Select the number of elements (data + header CAN FD message) in receive FIFO 1.	Auto allocate
Validate memory	Click Validate memory button to validate all the memory configurations.
Configure receive interrupt sources	Select this option to display receive interrupt sources for configuration.	off
Configure RX buffer interrupt sources	Select this option to display buffer interrupt sources for configuration.	off
Dedicated RX buffer message	Select the dedicated interrupt line for receive buffer message.	Disable
High priority message	Select the dedicated interrupt line for high priority message.	Disable
Configure RX FIFO 0 interrupt sources	Select this option to display receive FIFO 0 interrupt sources for configuration.	off
RX FIFO 0 new message	Select the interrupt line for receive FIFO 0 new message.	Disable
RX FIFO 0 full	Select the interrupt line for receive FIFO 0 full.	Disable
RX FIFO 0 message lost	Select the interrupt line for receive FIFO 0 message lost.	Disable
RX FIFO 0 watermark	Select the interrupt line for receive FIFO 0 watermark.	Disable
Configure RX FIFO 1 interrupt sources	Select this option to display receive FIFO 1 interrupt sources for configuration.	off
RX FIFO 1 new message	Select the interrupt line for receive FIFO 1 new message.	Disable
RX FIFO 1 full	Select the interrupt line for receive FIFO 1 full.	Disable
RX FIFO 1 message lost	Select the interrupt line for receive FIFO 1 message lost.	Disable
RX FIFO 1 watermark	Select the interrupt line for receive FIFO 1 watermark.	Disable
Configure transmit interrupt sources	Select this option to display transmit interrupt sources for configuration.	off
Configure TX FIFO interrupt sources	Enable to configure the transmit FIFO interrupt sources.	off
Transmission complete	Select the transmission interrupt line for transfer complete.	Disable
Transmission cancellation finish	Select the transmission interrupt line for transfer cancellation finish.	Disable
TX FIFO empty	Select the transmission interrupt line for TX FIFO empty.	Disable
Configure TX event FIFO interrupt sources	Select this option to display transmit event FIFO interrupt sources for configuration.	off
TX event FIFO new entry	Select the transmission interrupt line for TX event FIFO new entry.	Disable
TX event FIFO element lost	Select the transmission interrupt line for TX event FIFO element lost.	Disable
TX event FIFO full	Select the transmission interrupt line for TX event FIFO full.	Disable
TX event FIFO watermark	Select the transmission interrupt line for TX event FIFO watermark.	Disable
Configure other interrupt sources	Select this option to display other interrupt sources for configuration.	off
Timestamp wraparound	Select the interrupt line for timestamp wraparound interrupt.	Disable
Timeout occurred	Select the interrupt line for timeout occurred interrupt.	Disable
Error logging overflow	Select the interrupt line for error logging overflow interrupt.	Disable
Warning status	Select the interrupt line for warning status interrupt.	Disable
Watchdog event	Select the interrupt line for watchdog event interrupt.	Disable
Data protocol error	Select the interrupt line for data protocol error interrupt.	Disable
Message RAM access failure	Select the interrupt line for message RAM access failure interrupt.	Disable
Bit error uncorrected	Select the interrupt line for bit error uncorrected interrupt.	Disable
Error passive status	Select the interrupt line for error passive status interrupt.	Disable
Bus off status	Select the interrupt line for bus off status interrupt.	Disable
Arbitration protocol error	Select the interrupt line for arbitration protocol error interrupt.	Disable
Reserved address access	Select the interrupt line for reserved address access interrupt.	Disable

For more information on selecting a hardware board and general configuration settings, see Hardware Implementation Pane.