Simulate and analyze performance metrics of analog to digital data converters. Start from complete system-level models of typical ADC architectures, such as SAR or flash ADC. Modify ADC parameters until you reach your desired system specifications. Use Measurements and Testbenches to validate your design.
|Sampling Clock Source||Generate clock signal with aperture jitter|
|Delta Sigma Modulator||Model a discrete delta sigma modulator based ADC|
ADC Reference Architectures
DAC Reference Architectures
|Binary Weighted DAC||N-bit DAC based on R-2R weighted resistor architecture|
|Segmented DAC||Convert large digital input to analog signal using arrangement of smaller DACs|
- Compare SAR ADC to Ideal ADC
This example shows a comparison of the SAR ADC from the Mixed-Signal Blockset™ to the ideal ADC model with impairments presented in Analyzing Simple ADC with Impairments.
- Design and Evaluate Interleaved ADC Using System Object
This example shows how to use System Objects to model and evaluate the performance of an interleaved ADC.
- Effect of Metastability Impairment in Flash ADC
This example shows how to customize a flash Analog to Digital Converter (ADC) by adding the metastability probability as an impairment.
- Compare Binary Weighted DAC to Ideal DAC
This example shows a comparison of the Binary Weighted DAC from the Mixed-Signal Blockset™ to an ideal DAC model.
- Delta Sigma Modulator Data Converter with Half-Band Filter for Decimation
Use the delta sigma modulator data converter for an analog-to-digital converter application.