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Using Triggered Subsystems for HDL Code Generation

The Triggered Subsystem block is a Subsystem block that executes each time the control signal has a trigger value. To learn more about the block, see Triggered Subsystem.

Best Practices

When using triggered subsystems in models targeted for HDL code generation, consider the following:

  • For synthesis results to match Simulink® results, drive the trigger port with registered logic (with a synchronous clock) on the FPGA.

  • It is good practice to put unit delays on Triggered Subsystem output signals. Doing so prevents the code generator from inserting extra bypass registers in the HDL code.

  • The use of triggered subsystems can affect synthesis results in the following ways:

    • In some cases, the system clock speed can drop by a small percentage.

    • Generated code uses more resources, scaling with the number of triggered subsystem instances and the number of output ports per subsystem.

Using the Signal Builder Block

When you connect outputs from a Signal Builder block to a triggered subsystem, you might need to use a Rate Transition block. To run all triggered subsystem ports at the same rate:

  • If the trigger source is a Signal Builder block, but the other triggered subsystem inputs come from other sources, insert a Rate Transition block into the signal path before the trigger input.

  • If all inputs (including the trigger) come from a Signal Builder block, they have the same rate, so special action is not required.

Using Trigger As Clock

Using the trigger as clock in triggered subsystems enables you to partition your design into different clock regions in the generated code. Make sure that the Clock edge setting in the Configuration Parameters dialog box matches the Trigger type of the Trigger block inside the triggered subsystem.

For example, you can model:

  • A design with clocks that run at the same rate, but out of phase.

  • Clock regions driven by an external or internal clock divider.

  • Clock regions driven by clocks whose rates are not integer multiples of each other.

  • Internally generated clocks.

  • Clock gating for low-power design.

Note

Using the trigger as clock for triggered subsystems can result in timing mismatches of one cycle during testbench simulation.

Specify Trigger As Clock

  • In HDL Code Generation > Global Settings > Ports tab, select Use trigger signal as clock.

  • Set the TriggerAsClock property using makehdl or hdlset_param. For example, to generate HDL code that uses the trigger signal as clock for triggered subsystems in a DUT subsystem, myDUT, in a model, myModel, enter:

    makehdl ("myModel/myDUT",TriggerAsClock="on")

Trigger As Clock Without Synchronous Registers

When you use the trigger as clock in triggered subsystem, each triggered subsystem input or output requires synchronization delays immediately outside and immediately inside the subsystem. These delays act as a synchronization interface between the regions running at different rates. HDL Coder™ can allows you to generate HDL code without adding the synchronization delays by enabling the "trigger as clock without synchronous register" option. By default, this option is on.

You can enable or disable this option by using makehdl or hdlset_param function. For example, to generate an HDL code for a DUT subsystem, myDUT in a model, myModel, that uses trigger as a clock for triggered subsystem without having synchronization delays, enter:

makehdl("myModel/myDUT",TriggerAsClockWithoutSyncRegisters="on")

Use Triggered Subsystem for Asynchronous Clock Domain

Using triggered subsystem, you can design a model for asynchronous clock domain. An asynchronous clock domain design operates at different clock regions whose clock rates are not integer multiples of each other. You can model an asynchronous clock domain design in Simulink by using multiple triggered subsystem and use trigger as a clock functionality to generate separate clock signal for each triggered subsystem.

For example, the figure shows a DUT subsystem that has two triggered subsystem. Each subsystem is driven by the separate clock connected to the trigger port of triggered subsystem.

Simulink model with two triggered subsystem

You can enable Use trigger signal as a clock option for DUT subsystem and generate HDL Code. HDL Coder generates two clock ports, Clk1 and Clk2, for the DUT subsystem which are mapped to trigger port of triggered subsystems.

ENTITY DUT_Subsystem IS
  PORT( Clk2       :   IN    std_logic;
        Clk1       :   IN    std_logic;
        Data       :   IN    std_logic_vector(7 DOWNTO 0);  -- int8
        Out1       :   OUT   std_logic_vector(7 DOWNTO 0);  -- int8
        Out2       :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En6
        );
END DUT_Subsystem;
...
...

  u_Triggered_Subsystem1 : Triggered_Subsystem1
    PORT MAP( Trigger => Clk2,
              In1 => Data,  -- int8
              Out1 => Triggered_Subsystem1_out1  -- int8
              );

  u_Triggered_Subsystem : Triggered_Subsystem
    PORT MAP( Trigger => Clk1,
              In1 => Data,  -- int8
              Out1 => Triggered_Subsystem_out1  -- sfix16_En6
              );
...

In the HDL code for triggered subsystem, the trigger signals are used as clock as shown in code snippet below. You can use these clock signals to operate the subsystems at different clock rates.

ENTITY Triggered_Subsystem IS
  PORT( Trigger    :   IN    std_logic;
        In1        :   IN    std_logic_vector(7 DOWNTO 0);  -- int8
        Out1       :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En6
        );
END Triggered_Subsystem;
...
...
  Out1_hold_process : PROCESS (Trigger)
  BEGIN
    IF Trigger'EVENT AND Trigger = '1' THEN
      Gain_out1_hold <= Gain_out1;
    END IF;
  END PROCESS Out1_hold_process;
...

Use Triggered and Resettable Subsystem to Model Clock and Reset Signals

You can model control signals, such as clock and reset, by using the triggered and resettable subsystem. You can use trigger as clock functionality to model trigger port from triggered subsystem as a clock and use resettable subsystem to model reset port from Simulink.

When you use triggered or resettable subsystem in your model targeted for HDL code generation, you can:

  • Model a clock and reset signal from Simulink by including a resettable subsystem inside the triggered subsystem.

  • Use a triggered subsystem with synchronous semantics.

  • Generate a code with a single clock and reset for a nested resettable subsystem inside a triggered subsystem by using Trigger as a clock and Minimize global reset functionality.

  • Generate code that has multiple clock and reset signals for a model consisting of multiple triggered and resettable subsystem.

  • Generate an asynchronous reset port from a resettable subsystem by enabling the AsyncResetPort name-value argument of the makehdl function.

  • Use Unit Delay Enabled Synchronous block inside the Triggered subsystem.

  • Model a Unit Delay Resettable Synchronous block in the triggered subsystem by adding the Unit Delay block to a resettable subsystem with synchronous semantics and placing the resettable subsystem inside triggered subsystem.

  • Model a Unit Delay Enabled Resettable Synchronous block in the triggered subsystem by adding the Unit Delay Enabled block to a resettable subsystem with synchronous semantics and placing the resettable subsystem inside triggered subsystem.

For example, figure shows a model that has resettable subsystem placed within the triggered subsystem.

Asynchronous clock and reset using triggered and resettable subsystem

You can use trigger as clock functionality to model trigger port from triggered subsystem as a clock and use resettable subsystem to model reset port from Simulink. To enable trigger as clock, select Use trigger signal as a clock from HDL Code Generation > Global Settings > Ports tab in the Configuration Parameter Dialog box. Also, select Minimize global resets to minimize the generation of global reset port. The generated code for a model is shown in code snippet below.

ENTITY Subsystem IS
  PORT( Clk1           :   IN    std_logic;
        Data           :   IN    std_logic_vector(7 DOWNTO 0);  -- uint8
        Clk2           :   IN    std_logic;
        Reset1         :   IN    std_logic;
        Reset2         :   IN    std_logic;
        Out2           :   OUT   std_logic_vector(7 DOWNTO 0)  -- uint8
        );
END Subsystem;
...
...

  u_Triggered_Subsystem : Triggered_Subsystem
    PORT MAP( Trigger => Clk1,
              data => Data,  -- uint8
              reset1 => Reset1,
              Out1 => Triggered_Subsystem_out1  -- uint8
              );

  u_Triggered_Subsystem1 : Triggered_Subsystem1
    PORT MAP( Trigger => Clk2,
              data => Triggered_Subsystem_out1,  -- uint8
              reset2 => Reset2,
              Out1 => Triggered_Subsystem1_out1  -- uint8
              );
...
You can see that two reset signals, Reset1 and Reset2, are generated in the top-level subsystem, which are mapped to the reset port of the resettable subsystem.

The clock signals, Clk1 and Clk2, are mapped to the trigger port. These trigger signals are used as a clock in the generated HDL code.

Limitations

HDL Coder supports HDL code generation for triggered subsystems that meet the following conditions:

  • The triggered subsystem is not the DUT.

  • The subsystem is not both triggered and enabled.

  • The trigger signal is a scalar.

  • If the output of the subsystem is a bus then initial value of the outport must be 0.

  • All inputs and outputs of the triggered subsystem (including the trigger signal) run at the same rate.

  • The Show output port parameter of the Trigger block is set to Off.

  • The Latch input by delaying outside signal check box is not selected on the Inport block inside the Triggered Subsystem.

  • If the DUT contains the following blocks, RAMArchitecture is set to WithClockEnable:

    • Dual Port RAM

    • Simple Dual Port RAM

    • Single Port RAM

  • The triggered subsystem does not contain the following blocks:

    • Discrete-Time Integrator

    • CIC Decimation

    • CIC Interpolation

    • FIR Decimation

    • FIR Interpolation

    • Downsample

    • Upsample

    • HDL Cosimulation blocks for HDL Verifier™

    • Rate Transition

    • Pixel Stream FIFO (Vision HDL Toolbox™)

    • PN Sequence Generator, if the Use trigger signal as clock option is selected.