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makehdl

Generate HDL RTL code from model, subsystem, or model reference

Description

example

makehdl(dut) generates HDL code from the specified DUT model, subsystem, or model reference.

Note

Running this command can activate the Open at simulation start setting for blocks such as the Scope block and therefore invoke the block.

example

makehdl(dut,Name,Value) generates HDL code from the specified DUT model, subsystem, or model reference with options specified by one or more name-value pair arguments.

Examples

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This example shows how to generate VHDL for the symmetric FIR model.

Open the sfir_fixed model.

sfir_fixed

Generate HDL code for the current model with code generation options set to default values.

makehdl('sfir_fixed/symmetric_fir','TargetDirectory','C:\GenVHDL\hdlsrc')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as C:\GenVHDL\hdlsrc\sfir_fixed\symmetric_fir.vhd.
### Creating HDL Code Generation Check Report file://C:\GenVHDL\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated VHDL code is saved in the hdlsrc folder.

Generate Verilog® for the subsystem symmetric_fir within the model sfir_fixed.

Open the sfir_fixed model.

sfir_fixed;

The model opens in a new Simulink® window.

Generate Verilog for the symmetric_fir subsystem.

makehdl('sfir_fixed/symmetric_fir', 'TargetLanguage', 'Verilog', ...
               'TargetDirectory', 'C:/Generate_Verilog/hdlsrc')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as C:\Generate_Verilog\hdlsrc\sfir_fixed\symmetric_fir.v.
### Creating HDL Code Generation Check Report file://C:\Generate_Verilog\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated Verilog code for the symmetric_fir subsystem is saved in hdlsrc\sfir_fixed\symmetric_fir.v.

Close the model.

bdclose('sfir_fixed');

Check that the subsystem symmetric_fir is compatible with HDL code generation, then generate HDL.

Open the sfir_fixed model.

sfir_fixed

The model opens in a new Simulink® window.

Use the checkhdl function to check whether the symmetric_fir subsystem is compatible with HDL code generation.

hdlset_param('sfir_fixed','TargetDirectory','C:/HDL_Checks/hdlsrc');
checkhdl('sfir_fixed/symmetric_fir')
### Starting HDL check.
### Creating HDL Code Generation Check Report file://C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.

checkhdl completed successfully, which means that the model is compatible for HDL code generation. To generate code, use makehdl

makehdl('sfir_fixed/symmetric_fir')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('sfir_fixed', { 'HDL Code Generation' } )">sfir_fixed</a> for HDL code generation parameters.
### Starting HDL check.
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir.vhd.
### Creating HDL Code Generation Check Report file://C:\HDL_Checks\hdlsrc\sfir_fixed\symmetric_fir_report.html
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

The generated VHDL® code for the symmetric_fir subsystem is saved in hdlsrc\sfir_fixed\symmetric_fir.vhd.

Close the model.

bdclose('sfir_fixed');

Input Arguments

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Specified as subsystem name, top-level model name, or model reference name with full hierarchical path.

Example: 'top_level_name'

Example: 'top_level_name/subsysA/subsysB/codegen_subsys_name'

Name-Value Pair Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside quotes. You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Example: 'TargetLanguage','Verilog'
Target Language and Folder Selection Options

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Specify the Subsystem in your model to generate HDL code for. For more information, see Generate HDL for.

Specify whether to generate VHDL or Verilog code. For more information, see Language.

Specify a path to write the generated files and HDL code into. For more information, see Folder.

Tool and Synthesis Options

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Specify the synthesis tool for targeting the generated HDL code as a character vector. For more information, see Synthesis Tool.

Specify the synthesis tool chip family for the target device as a character vector. For more information, see Family.

Specify the synthesis tool device name for the target device as a character vector. For more information, see Device.

Specify the synthesis tool package name for the target device as a character vector. For more information, see Package.

Specify the synthesis tool speed value for the target device as a character vector. For more information, see Speed.

Specify the target frequency in MHz as a character vector. For more information, see Target Frequency Parameter.

General Optimizations and Multicycle Path Constraints Settings

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Specify whether to enable delay balancing on the model. For more information, see Balance delays.

Specify, in bits, the minimum RAM size required for mapping to RAMs instead of registers. For more information, see RAM mapping threshold (bits).

Specify whether to map pipeline registers in the generated HDL code to block RAMs on the FPGA. For more information, see Map pipeline delays to RAM.

Specify whether to transform Delay blocks that have nonzero initial value to Delay blocks that have a zero initial value. For more information, see Transform non zero initial value delay.

Partition multipliers in the design based on a threshold value. The threshold must be a positive integer value, N. For more information, see Multiplier partitioning threshold.

Generate a multicycle path constraints text file. For more information, see Register-to-register path info.

Generate an enable-based multicycle path constraints file. For more information, see Enable based constraints.

Pipelining and Speed Optimization Options

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Specify whether to prioritize the distributed pipelining optimization for numerical integrity or performance. For more information, see Distributed pipelining priority.

Apply the hierarchical distributed pipelining optimization on the model to move delays across hierarchies. For more information, see Hierarchical distributed pipelining.

Distribute design delays in your model. For more information, see Preserve design delays.

Insert pipeline registers at the clock rate or the data rate. For more information, see Clock-rate pipelining.

Enable clock-rate pipelining for DUT ports. For more information, see Allow clock-rate pipelining of DUT output ports.

Insert adaptive pipeline registers in your design. For more information, see Adaptive pipelining.

Resource Sharing and Area Optimization Options

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Use resource sharing optimization to share adders in your design. For more information, see Share Adders.

Minimum bitwidth of a shared adder for the resource sharing optimization, specified as a positive integer. For more information, see Adder sharing minimum bitwidth.

Use resource sharing optimization to share multipliers in your design. For more information, see Share Multipliers.

Minimum bitwidth of a shared multiplier for the resource sharing optimization, specified as a positive integer. For more information, see Multiplier sharing minimum bitwidth.

Minimum wordlength by which the code generator promotes a multiplier for sharing with other multipliers. For more information, see Multiplier promotion threshold.

Use resource sharing optimization to share Multiply-Add blocks in your design. For more information, see Share Multipliers.

Minimum bitwidth of a shared Multiply-Add block for the resource sharing optimization, specified as a positive integer. For more information, see Multiply-Add block sharing minimum bitwidth.

Use resource sharing optimization to share Atomic Subsystem blocks in your design. For more information, see Share Atomic subsystems.

Use resource sharing optimization to share MATLAB Function blocks in your design. For more information, see Share MATLAB Function blocks.

Use resource sharing optimization to share floating-point IPs in your design. For more information, see Share Floating-Point IPs.

Floating Point Target

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For more information, see Floating Point IP Library.

Code Generation Report Options

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Generate a traceability report that has hyperlinks for navigating from code-to-model and from model-to-code. For more information, see Generate traceability report.

Generate a traceability report that has hyperlinks from each line or to a comment indicating block of code for navigating from code-to-model and from model-to-code. For more information, see Traceability style.

Generate a resource utilization report that displays the number of hardware resources that the generated HDL code uses. For more information, see Generate resource utilization report.

Generate an optimization report that displays the effect of optimizations such as streaming, sharing, and distributed pipelining. For more information, see Generate optimization report.

Generate a web view of the model in the Code Generation report to easily navigate between the code and model. For more information, see Generate model Web view.

Clock Settings

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Specify whether to use synchronous or asynchronous reset in the generated HDL code. For more information, see Reset type.

Specify whether to use an active-high or active-low asserted level for the reset input signal. For more information, see Reset asserted level.

Specify the clock input port name as a character vector. For more information, see Clock input port.

Specify the clock enable input port name as a character vector. For more information, see Clock enable input port.

Reset input port name, specified as a character vector.

For more information, see Reset input port.

Specify the active clock edge for the generated HDL code. For more information, see Clock edge

Specify whether to generate single or multiple clock inputs in the HDL code. For more information, see Clock inputs.

Frequency of global oversampling clock, specified as an integer multiple of the model’s base rate. For more information, see Oversampling factor.

General File and Variable Name Options

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Specify comment lines in header of generated HDL and test bench files. For more information, see Comment in header.

Specify the file name extension for generated Verilog files. For more information, see Verilog file extension.

Specify the file name extension for generated VHDL files. For more information, see VHDL file extension.

Specify the postfix as a character vector that resolves duplicate entity or module names. For more information, see Entity conflict postfix.

Specify the postfix for the package file name as a character vector. For more information, see Package postfix.

For more information, see Reserved word postfix.

For more information, see Split entity and architecture.

For more information, see Split entity file postfix.

For more information, see Split arch file postfix.

For more information, see VHDL architecture name.

Specify the postfix for clocked process names as a character vector. For more information, see the Clocked process postfix section in Clock Settings and Timing Controller Postfix Parameters.

For more information, see Complex imaginary part postfix in Complex Signals Postfix Parameters.

For more information, see Complex real part postfix in Complex Signals Postfix Parameters.

Prefix for internal clock enable and control flow enable signals, specified as a character vector. For more information, see Clock Enable Settings and Parameters.

Specify a prefix for every module or entity name in the generated HDL code. HDL Coder™ also applies this prefix to generated script file names

For more information, see ModulePrefix in Language-Specific Identifiers and Postfix Parameters.

For more information, see Timing controller postfix in Clock Settings and Timing Controller Postfix Parameters.

For more information, see Pipeline postfix.

For more information, see VHDL library name.

For more information, see Block generate label.

For more information, see Output generate label.

For more information, see Instance generate label.

For more information, see Instance postfix.

For more information, see Instance prefix.

For more information, see Vector prefix.

For more information, see Map file postfix.

Configuration Options for Ports

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VHDL inputs can have 'std_logic_vector' or 'signed/unsigned' data type. Verilog inputs must be 'wire'.

For more information, see Input and Output Port and Clock Enable Output Type Parameters.

VHDL output can be 'Same as input data type', 'std_logic_vector' or 'signed/unsigned'. Verilog output must be 'wire'.

For more information, see Input and Output Port and Clock Enable Output Type Parameters.

Clock enable output port name, specified as a character vector.

For more information, see Clock Enable output port.

For more information, see Use trigger signal as clock.

For more information, see Scalarize ports.

Coding Style

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For more information, see Represent constant values by aggregates.

For more information, see Inline MATLAB Function block code.

For more information, see Initialize all RAM blocks.

For more information, see RAM Architecture.

For more information, see No-reset registers initialization.

For more information, see Minimize intermediate signals.

For more information, see Unroll for Generate Loops in VHDL code.

For more information, see Enumerated Type Encoding Scheme.

For more information, see Use "rising_edge/falling_edge" style for registers in RTL Style Parameters.

For more information, see Inline VHDL configuration.

For more information, see Concatenate type safe zeros.

Specify whether you want to obfuscate the generated HDL code. For more information, see Generate obfuscated HDL code.

For more information, see Optimize timing controller

For more information, see Timing controller architecture

For more information, see Custom File Header Comment.

For more information, see Custom File Footer Comment.

For more information, see Emit time/date stamp in header in RTL Annotation Parameters.

For more information, see Include requirements in block comments.

For more information, see Use Verilog `timescale directives.

For more information, see Verilog timescale specification.

Coding Standards

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Specify whether the generated HDL code must conform to the Industry coding standard guidelines. For more information, see Choose Coding Standard and Report Option Parameters.

Coding standards customization object to use with the Industry coding standard when generating HDL code. For more information, see hdlcoder.CodingStandard.

Model Generation Parameters

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For more information, see Generated model.

For more information, see Validation model.

For more information, see Prefix for generated model name.

For more information, see Suffix for validation model name.

For more information, see Auto block placement.

For more information, see Auto signal routing.

For more information, see Inter-block horizontal scaling.

For more information, see Inter-block vertical scaling.

Diagnostics and Code Generation Output Parameters

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Specify whether to highlight feedback loops in your design. For more information, see Highlight feedback loops inhibiting delay balancing and optimizations.

Specify whether to highlight barriers for clock-rate pipelining optimization. For more information, see Highlight blocks inhibiting clock-rate pipelining.

Specify whether you want to generate HDL code, or only display the generated model, or generate HDL code and display the generated model. For more information, see the Generate HDL code section in Code Generation Output Parameter.

Generate HDL code for the model. For more information, see the Generate HDL code section in Code Generation Output Parameter.

Script Generation

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For more information, see Generate EDA scripts.

For more information, see Compile initialization.

For more information, see Compile termination.

For more information, see Compile file postfix.

Verilog compilation command, specified as a character vector. The SimulatorFlags name-value pair specifies the first argument, and the module name specifies the second argument.

For more information, see Compile command for Verilog.

VHDL compilation command, specified as a character vector. The SimulatorFlags name-value pair specifies the first argument, and the entity name specifies the second argument.

For more information, see Compile command for VHDL.

For more information, see Choose HDL lint tool.

HDL lint initialization name, specified as a character vector. The default is derived from the HDLLintTool name-value pair.

For more information, see Lint initialization.

HDL lint command, specified as a character vector. The default is derived from the HDLLintTool name-value pair.

For more information, see Lint command.

HDL lint termination, specified as a character vector. The default is derived from the HDLLintTool name-value pair.

For more information, see Lint termination.

For more information, see Choose synthesis tool.

HDL synthesis command, specified as a character vector. The default is derived from the HDLSynthTool name-value pair.

For more information, see Synthesis command.

HDL synthesis script file name postfix, specified as a character vector. The default is derived from the HDLSynthTool name-value pair.

For more information, see Synthesis file postfix.

Initialization for the HDL synthesis script, specified as a character vector. The default is derived from the HDLSynthTool name-value pair.

For more information, see Synthesis initialization.

Termination name for the HDL synthesis script. The default is derived from the HDLSynthTool name-value pair.

For more information, see Synthesis termination.

Introduced in R2006b