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Simulink Real-Time FPGA I/O Modules

Generate and deploy HDL code on Simulink® Real-Time™ FPGA I/O Modules (requires Simulink Real-Time)

You can generate an FPGA programming file and Simulink Real-Time FPGA I/O interface for deployment on a Speedgoat® I/O module. See IP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules.


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hdlcoder.BoardBoard registration object that describes SoC custom board
hdlcoder.WorkflowConfigConfigure HDL code generation and deployment workflows
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design


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socExportReferenceDesignExport custom reference design for HDL Workflow Advisor (Since R2020a)
addExternalIOInterfaceDefine external IO interface for board object
addExternalPortInterfaceDefine external port interface for board object
addInternalIOInterfaceAdd and define internal IO interface between generated IP core and existing IP cores
addAXI4MasterInterfaceAdd and define AXI4 Master interface
addAXI4SlaveInterfaceAdd and define AXI4 slave interface
addAXI4StreamInterfaceAdd AXI4-Stream interface (Since R2020a)
addAXI4StreamVideoInterfaceAdd AXI4-Stream Video interface (Since R2020a)
addClockInterfaceAdd clock and reset interface
addCustomEDKDesignSpecify Xilinx EDK MHS project file
addCustomQsysDesignSpecify Altera Qsys project file
addCustomVivadoDesignSpecify Xilinx Vivado exported block design Tcl file
addIPRepositoryInclude IP modules from your IP repository folder in your custom reference design
addParameterAdd and define custom parameters for your reference design
validateReferenceDesignCheck property values in reference design object
validateBoardCheck property values in board object



Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.