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PIL(Processor-in-the-Loop) 시뮬레이션
PIL(Processor-in-the-Loop) 시뮬레이션은 생성된 소스 코드를 크로스 컴파일한 다음 타깃 하드웨어에 오브젝트 코드를 다운로드하여 실행합니다. 일반 시뮬레이션 결과와 PIL 시뮬레이션 결과를 비교하여 모델과 생성된 코드의 수치적 동등성을 테스트할 수 있습니다. PIL 시뮬레이션 동안 생성된 코드에 대한 코드 커버리지와 실행 시간 메트릭을 수집할 수 있습니다.
PIL 시뮬레이션에는 연결 구성이 필요합니다.
앱
| SIL/PIL 관리자 | Verify generated code |
네임스페이스
target | Manage target hardware and build tool information |
클래스
객체
함수
도움말 항목
- SIL and PIL Simulations
An overview of software-in-the-loop (SIL) and processor-in-the-loop simulations (PIL).
- Choose a SIL or PIL Approach
Test code generated from top models, referenced models, or subsystems.
- Create PIL Target Connectivity Configuration for Simulink
Customize PIL simulation for your target environment.
- Host-Target Communication for Simulink PIL Simulation
Use the
rtiostreamAPI for communication between your development computer and target hardware during a PIL simulation. - Specify Hardware Timer for Simulink
Specify a hardware timer using the Code Replacement Tool.
- Set Up PIL Connectivity by Using Target Framework
Provide PIL connectivity between Simulink® and the target hardware.
- Custom Toolchain Directives Required for Code Coverage and Execution Profiling
Specify compiler directives for building PIL application that supports code coverage analysis and execution profiling.
- Configure and Run PIL Simulation
Set up and run top-model PIL, Model block PIL, and PIL block simulations.
- Unit Test Subsystem Code with SIL/PIL Manager
Perform unit testing on atomic subsystem by using SIL/PIL Manager.
- SIL/PIL Manager Verification Workflow
A simplified workflow for verifying generated code.
- PIL Simulation Sequence
How a PIL simulation proceeds.
- Simulation Mode Override Behavior in Model Reference Hierarchy
How the simulation mode of the top model or parent model determines the simulation behavior of a model hierarchy.
- Field-Oriented Control of Permanent Magnet Synchronous Machine
Simulate motor control system, generate controller code, and use PIL simulation to test numerical equivalence and profile code execution times.
- Security for PIL Simulations
Security measures for PIL simulations.
- SIL and PIL Limitations
Modeling and code generation features that are not supported or partially supported by SIL and PIL simulations.
문제 해결
Debug Generated Code During SIL or PIL Simulation
Use a debugger to understand the behavior of generated code.
View SIL and PIL Files in Code Generation Report
Produce a code generation report and static code metrics that cover SIL and PIL files.
Verification of Code Generation Assumptions
The SIL or PIL simulation checks code generation assumptions.
추천 예제
Test Generated Code with SIL and PIL Simulations
Use software-in-the-loop (SIL) and processor-in-the-loop (PIL) simulations to test numerical equivalence between model components and generated code.
Configure Processor-In-The-Loop (PIL) for a Custom Target
Create target connectivity configuration and run PIL simulation.
Create a Target Communication Channel for Processor-in-the-Loop (PIL) Simulation
Use rtiostream interface to provide a communication channel
for PIL simulations.
