HDL Coder™ provides additional configuration options that affect HDL
implementation and synthesized logic.
HDL code for the Sample and Hold block is generated as a
Triggered Subsystem. Similar restrictions apply to both blocks.
See Using Triggered Subsystems for HDL Code Generation (HDL Coder).
Best PracticesWhen using the Sample and Hold block in models targeted for HDL
code generation, consider the following:
For synthesis results to match Simulink® results, drive the trigger port with registered logic
(with a synchronous clock) on the FPGA.
It is good practice to put a unit delay on the output signal. Doing
so prevents the code generator from inserting extra bypass registers in
the HDL code.
The use of triggered subsystems, such as the Sample and
Hold block, can affect
synthesis results in the following ways:
In some cases, the system clock speed can drop by a small
percentage.
Generated code uses more resources, scaling with the number of
triggered subsystem instances.
RestrictionsThe Sample and Hold block must meet the following
conditions:
The DUT (i.e., the top-level subsystem for which code is generated)
must not be the Sample and Hold block.
The trigger signal must be a scalar.
The data type of the trigger signal must be either
boolean
or ufix1
.
The output of the Sample and Hold block must have an
initial value of 0.
The input, output, and trigger signal of the Sample and
Hold block must run at the same rate. If one of the input or
the trigger signals is an output of a Signal Builder
block, see Using the Signal Builder Block (HDL Coder)
for how to match rates.