M-PSK Demodulator Baseband

Demodulate PSK-modulated data

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Libraries:
Communications Toolbox / Modulation / Digital Baseband Modulation / PM
Communications Toolbox HDL Support / Modulation / PM

Description

The M-PSK Demodulator Baseband block demodulates a baseband representation of a PSK-modulated signal. The modulation order, M, is equivalent to the number of points in the signal constellation and is determined by the M-ary number parameter. The block accepts scalar or column vector input signals.

Examples

Modulate and Demodulate 8-PSK Signal

Use the Open model button to open the doc_8psk_model model. The model generates an 8-PSK signal, applies white noise, displays the resulting constellation diagram, and computes the error statistics.

Open Model

Ports

Input

Port_1 — Input signal

scalar | vector

Input port accepting a baseband representation of a PSK-modulated signal.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean

Output

Port_1 — Output signal

scalar | vector

Output signal, returned as a scalar or vector. The output is a demodulated version of the PSK-modulated signal.

Data Types: single | double | fixed point

Parameters

M-ary number — Modulation order of the PSK constellation

8 (default) | scalar

Specify the modulation order as a positive integer power of two.

Example: 2 | 16

Output type — Output signal data type

Integer (default) | Bit

Specify the elements of the input signal as integers or bits. If Output type is Bit, the number of samples per frame is an integer multiple of the number of bits per symbol, log₂(M).

Decision type — Demodulator output

Hard decision (default) | Log-likelihood ratio | Approximate log-likelihood ratio

Specify the demodulator output to be hard decision, log-likelihood ratio (LLR), or approximate LLR. The LLR and approximate LLR outputs are used with error decoders that support soft-decision inputs such as a Viterbi Decoder, to achieve superior performance. This parameter is available when Output type is Bit.

See Phase Modulation for algorithm details. The output values for Log-likelihood ratio and Approximate log-likelihood ratio decision types are of the same data type as the input values

Noise variance source — Source of noise variance

Dialog (default) | Port

Specify the source of the noise variance estimate. This parameter is available when Decision type is Log-likelihood ratio or Approximate log-likelihood ratio.

• To specify the noise variance from the dialog box, select Dialog.

• To input the noise variance from an input port, select Port.

Noise variance — Estimate of noise variance

1 (default) | positive scalar

Specify the estimate of the noise variance as a positive scalar. This parameter is available when Noise variance source is Dialog.

This parameter is tunable in all simulation modes. If you use the Simulink^® Coder™ rapid simulation (RSIM) target to build an RSIM executable, then you can tune the parameter without recompiling the model. Avoiding recompilation is useful for Monte Carlo simulations in which you run the simulation multiple times (perhaps on multiple computers) with different amounts of noise.

Note

The exact LLR algorithm computes exponentials using finite precision arithmetic. Computation of exponentials with very large positive or negative magnitudes might yield:

• Inf or -Inf if the noise variance is a very large value

• NaN if both the noise variance and signal power are very small values

When the output returns any of these values, try using the approximate LLR algorithm because it does not compute exponentials.

Constellation ordering — Symbol mapping

Gray (default) | Binary | User-defined

Specify how the integer or group of log₂(M) bits is mapped to the corresponding symbol.

• When Constellation ordering is set to Gray, the output symbol is mapped to the input signal using a Gray-encoded signal constellation.

• When Constellation ordering is set to Binary, the modulated symbol is exp(jϕ+j2πm/M), where ϕ is the phase offset in radians, m is the integer output such that 0 ≤ m ≤ M – 1, and M is the modulation order.

• When Constellation ordering is User-defined, specify a vector of size M, which has unique integer values in the range [0, M–1]. The first element of this vector corresponds to the constellation point having a value of e^jϕ with subsequent elements running counterclockwise.

Example: [0 3 2 1]

Constellation mapping — User-defined symbol mapping

[0:7] (default) | vector

Specify the order in which input integers are mapped to output integers. The parameter is available when Constellation ordering is User-defined, and must be a row or column vector of size M having unique integer values in the range [0, M – 1].

The first element of this vector corresponds to the constellation point at 0 + Phase offset angle, with subsequent elements running counterclockwise. The last element corresponds to the -2π/M + Phase offset constellation point.

Phase offset (rad) — Phase offset in radians

pi/8 (default) | scalar

Specify, in radians, the phase offset of the initial constellation as a real scalar.

Example: pi/4

Output data type — Output data type

Inherit via internal rule (default) | Smallest unsigned integer | double | single | int8 | uint8 | int16 | uint16 | int32 | uint32

Specify the data type of the demodulated output signal.

Block Characteristics

Data Types	Boolean | double | fixed pointa, b, c | integer | single
Multidimensional Signals	no
Variable-Size Signals	yes
a M = 2, 4, 8 only. b Fixed-point inputs must be signed. c When ASIC/FPGA is selected in the Hardware Implementation Pane, output is ufix(1) for bit outputs, and ufix(ceil(log2(M))) for integer outputs.

Algorithms

Hard-Decision BPSK Demodulation

The signal preprocessing required for BPSK demodulation depends on the configuration.

This figure shows the hard-decision BPSK demodulation signal diagram for the trivial phase offset (multiple of π/2) configuration.

This figure shows the hard-decision BPSK demodulation floating-point signal diagram for the nontrivial phase offset configuration.

This figure shows the hard-decision BPSK demodulation fixed-point signal diagram for the nontrivial phase offset configuration.

Hard-Decision QPSK Demodulation

The signal preprocessing required for QPSK demodulation depends on the configuration.

This figure shows the hard-decision QPSK demodulation signal diagram for the trivial phase offset (odd multiple of π/4) configuration.

This figure shows the hard-decision QPSK demodulation floating-point signal diagram for the nontrivial phase offset configuration.

This figure shows the hard-decision QPSK demodulation fixed-point signal diagram for the nontrivial phase offset configuration.

Hard-Decision Higher-Order PSK

The signal preprocessing required for higher order PSK demodulation depends on the configuration.

This figure shows the hard-decision 8-PSK demodulation signal diagram for the trivial phase offset (odd multiple of π/8) configuration.

This figure shows the hard-decision 8-PSK demodulation fixed-point signal diagram for trivial phase offset (odd multiple of π/8) configuration.

This figure shows the hard-decision M-PSK demodulation floating-point signal diagram for the nontrivial phase offset configuration.

For M > 8, to improve speed and implementation costs, no derotation arithmetic is performed for trivial case (specifically, when phase offset is 0, π/2, π, or 3π/2).

Also, for M > 8, only double and single input types are supported.

Log-Likelihood Ratio and Approximate Log-Likelihood Ratio

The exact LLR and approximate LLR algorithms (soft-decision) are described in Phase Modulation.

References

[1] Proakis, John G. Digital Communications. 4th ed. New York: McGraw Hill, 2001.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced before R2006a