BPSK Modulator Baseband

Modulate using BPSK method

• 

Libraries:
Communications Toolbox / Modulation / Digital Baseband Modulation / PSK
Communications Toolbox HDL Support / Modulation / PM

Description

The BPSK Modulator Baseband block modulates a signal by using the binary phase shift keying (BPSK) method. The output is a baseband representation of the modulated signal. The input signal must be a discrete-time binary-valued signal. If the input bit is 0 or 1, then the modulated symbol is exp(jϕ) or -exp(jϕ), respectively. The Phase offset (rad) parameter specifies the value of ϕ in radians.

Examples

Cyclic Redundancy Check of Noisy BPSK Data Frames in Simulink

Use a CRC code to detect frame errors in a noisy BPSK signal.

In the cm_ex_crc_noisy_bpsk_frames model, the CRC generator and detector pair use a standard CRC-4 polynomial, . The length of the CRC is 4 bits as determined by the degree of the polynomial. The number of checksums per frame is 1, so the full transmission frame has one CRC appended at the end.

A binary signal frame gets a CRC code appended to the end of the frame. BPSK modulation is applied to the signal and the signal passes through an AWGN channel. The signal is demodulated, and then a CRC syndrome detector removes the CRC and calculates the CRC errors.

Generate 12-bit frames of binary data and append CRC bits. Based on the degree of the polynomial, 4 bits are appended to each frame. Apply BPSK modulation and pass the signal through an AWGN channel. Demodulate and use the CRC detector to determine if the frame is in error.

The results of the CRC detection are compared to a BER calculation.

Number of bit errors detected:  6
Number of crc errors detected:  7

Extended Examples

Frame Synchronization Using Barker Code Preamble

Use a length 13 Barker code frame preamble for frame synchronization of data bits.

• Open Model

Ports

Input

In — Input data

scalar | vector

Input signal, specified as a scalar or vector with element values in the range [0,1].

This port in unnamed on the block.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean

Output

Out — BPSK-modulated baseband signal

scalar | vector

BPSK-modulated baseband signal, returned as a complex-valued scalar or vector.

Data Types: single | double | fixed point

Parameters

To edit block parameters interactively, use the Property Inspector. From the Simulink^® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

Main

Phase offset (rad) — Phase offset of zeroth point

0 (default) | scalar

Phase offset of the zeroth point of the constellation in radians, specified as a scalar.

Example: pi/4

View constellation — Option to plot reference constellation

button

Click View Constellation on the block mask to visualize a signal constellation for the specified block parameters. Before viewing a constellation, apply the parameter settings. For more information, see View Constellation of Modulator Block.

Data Types

Output data type — Output data type

double (default) | single | fixdt(1,16) | fixdt(1,16,0) | Inherit via back propagation | <data type expression>

The output data type, specified as double, single, fixdt(1,16), fixdt(1,16,0), Inherit via back propagation, or <data type expression>.

Setting this parameter to

• fixdt(1,16), fixdt(1,16,0), or <data type expression> enables parameters in which you can further specify details.

• Inherit via back propagation sets the output data type and scaling to match the following block.

For information about specifying data types, see Data Type Assistant.

Block Characteristics

Data Types	Boolean | double | fixed pointa, b | integer | single
Multidimensional Signals	no
Variable-Size Signals	yes
a ufix(ceil(log2(M))) only at the input for M-ary modulation. b Fixed-point outputs must be signed.

More About

Data Type Assistant

The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant (Simulink).

Algorithms

Phase modulation is a linear baseband modulation technique in which the message modulates the phase of a constant amplitude signal. Binary Phase Shift Keying (BPSK) is a two phase modulation scheme, where the 0’s and 1’s in a binary message are represented by two different phase states in the carrier signal

$$s_n(t)=\sqrt{\frac{2E_b}{T_b}}\cos \left(2\pi f_{c}t+{\varphi }_n\right),$$

for $$(n-1)T_b\le t\le n{T}_b,\text{ n}=\text{1},\text{2},\text{ 3},\dots$$ where:

• ϕ_n = πm + ϕ, m∈{0,1}.

• ϕ is the initial phase offset.

• E_b is the energy per bit.

• T_b is the bit duration.

• f_c is the carrier frequency.

In MATLAB^®, the baseband representation of a BPSK signal is

$$s_n(t)=e^{-i{\varphi }_n}=\cos \left(\pi n\right).$$

The BPSK signal has two phases: 0 and π.

The probability of a bit error in an AWGN channel is

$$P_b=Q\left(\sqrt{\frac{2E_b}{N_0}}\right),$$

where N₀ is the noise power spectral density.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced before R2006a