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PMSM is programed in FPGA using HDL coder.
I think you are referring to this example. https://www.mathworks.com/videos/deploy-motor-control-algorithms-to-fpga-hardware-pro...

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Modeling S-R Flip flip for HDL code generation
Attached in an example model that works in 22a release.

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The top design unit selected for HDL code generation may not be inside a triggered subsystem.
The DUT targeted for code generation can be a whole model with root ports, or a regular virtual or atomic subystem, model refere...

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makehdltb. Dont open generated model.
I am assuming the act of simulation of your model opens scopes; HDL Coder simulates the model to collect stimulus and response o...

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What does 'coder.internal.indexShapeCheck>>errORWarnIF .... code generation assumption about size violated' mean?
This error is unexpected. Please share a sample project file that reproduces the error or reach out to technical support. HDL Co...

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How set block parameter over Zynq AXIS Lite bus?
https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-parameters.html Generate DUT Ports for Tunable Paramet...

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Zynq workflow error in step 4.2
This is an unepxected error issue. Please contact tech support for a solution and the next steps.

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how to solve this error?
Results from FPGA synthesis tool cannot be backannotated to model if they fall within Stateflow Block. This is a known limitatio...

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How to get list of all optimizations requested by subsystems in HDL Coder model?
>> hdlsaveparams('<path_to_the_dut>') >> help hdlsaveparams % PARAMETERSET = hdlsaveparams(DUT, FILENAME, FORCE_OVER...

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Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t
This is an unexpected error. Can you reach out MathWorks support team with the reproduction steps for a resolution and a worka...

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HDL coder error (Invalid feature 'ModelAdvisorGenerateNewStyleViewSwitchInGUI)
We are unable to reproduce this issue. Please contact local technical support for additional guidance.

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Workflow advisor synthesis error
Can you attach a sample project and design files to reproduce this error?

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Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...

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Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...

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[Matlab Coder] Generate C code with hierarchy
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

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Break-up of CLAHE algorithm such that HDL Coder can support it.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

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Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

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generation matlab to VHDL
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

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How to use Matlab generated c code for vivado HLS ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

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Compose High Level Synthesis (HLS) from Matlab code
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

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How to use Matlab generated c code for High Level Synthesis ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

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Generate C code for HLS?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...

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How to add a custom parameter in the generated module with HDL Coder,simulink?
How are generics supported in HDL Coder? https://www.mathworks.com/support/search.html/answers/382489-how-are-generics-supporte...

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HDL Code generation and deploy data onto the hardware board
For #1 Getting Started with Targeting Xilinx Zynq Platform https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-ha...

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HDL code generation of delay block and problem in regard to the use of verilog ce_out
A sample model would be helpful. I built one using the info shown in the picture above. Given there is a ratio of 5000 bet...

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In HDL Simulink, How to convert from integer to boolean array.
https://www.mathworks.com/help/hdlcoder/ref/bitslice.html >> hdlcoder_int2bits_bits2int You can check this thread as well....

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HDL supported block for integer to binary
can you try this example? >>hdlcoder_int2bits_bits2int

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Update Diagram fails on "No Connect" Cosim block
Can you share a sample model with your usecase?

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How to deploy matlab deep learning models to Texas Instruments?
DL code generated for library-free “none” target should be deployable on TI C2000. https://www.mathworks.com/videos/generate-...

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Vivado 2020.2 and HDL coder
HDL Coder generated VHDL/Verilog code is Vivado version independent and works with any version of the Xilinx software. For Viva...

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