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hw/sw Co-Design Workflow and UDP communication between Zynq zedboard and host computer
Hello everyone, I need help please, I'm trying to perform HW/SW Co-design for a zedboard. I have this simulink model: The subsy...
거의 7년 전 | 답변 수: 1 | 0
1
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Using direct lookup table as input to a matlab function block in simulink => error in "Check Block Compatibility" of "HDL Workflow Advisor"
Hello everyone, In my Simulink model I have a matlab function block, with the following code: function device_exist = look_4_...
대략 7년 전 | 답변 수: 1 | 0
1
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About hdlsllib/HDL RAMs blocks
hello everyone, Can you please tell me what is the difference between Port RAM blocks and Port RAM System blocks in the HDL Co...
대략 7년 전 | 답변 수: 2 | 0
2
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problem generating hdl ip core of statflow using hdl workflow advisor: can't run the 1.2 task Set Target Reference Design
hello friends, I need some help please, I'm designing an I2C slave using stetflow, to make an HDL IP Core out of it using HDL W...
대략 7년 전 | 답변 수: 1 | 0
1
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Error in default port dimensions function of S-function 'slaveV2/SlaveI2C/Chart'. This function does not fully set the dimensions of output port 3
hi everyone, I'm trying to design an I2C slave using stetflow, and then to make an IP Core generation of it using HDL Workflow...
대략 7년 전 | 답변 수: 0 | 0
0
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The hasChangedTo function in a stateflow chart applied to a boolean
Hi everyone, I would like to know if the hasChangedTo function can be applied to a stateflow data of type boolean (i.e logical)....
대략 7년 전 | 답변 수: 1 | 0
1
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About HDL simulink coder
Hello, Pham Van Dung and Kiran Kintali, I have the same error while trying to make an IP core generation of my design, compris...
About HDL simulink coder
Hello, Pham Van Dung and Kiran Kintali, I have the same error while trying to make an IP core generation of my design, compris...
대략 7년 전 | 0
