# Floating-points for HDL

조회 수: 3(최근 30일)
Joshua Ford 2021년 2월 16일
답변: Andy Bartlett 2021년 2월 16일
Hi,
Most documentation I have read on mathworks states that the model floating-points should be converted into fixed-points for generate HDL code and implement it on hardware. Will HDL coder work if model remains with floating-points? Can the same process and tools be applied and what are the consequences of not converting to fixed-point?
Thanks,
Josh

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### 답변(1개)

Andy Bartlett 2021년 2월 16일
HDL Coder is flexible with regard to types. It supports floating-point, fixed-point, and mixtures of the two.
The primary benefits to converting to fixed-point are reduced consumption of chip resources, reduced power consumption, and increased speed. A high percentage of embedded intent algorithms can be converted to fixed-point and can achieve significant efficiency improvements. The improvements can be the difference between a design that meets constraints or fails them.
Some algorithms are better left all or partially in floating-point. Typically, these algorithms require very high dynamic ranges for some signals or calculations. Floating-point will be more efficient for direct implementation of these cases.
For both floating-point and fixed-point, it is often useful to consider modifying the algorithmic approach to be more hardware friendly. One example is to replace a complex calculation with an optimized lookup table.
Another example is to restructure to avoid tricky calculations like matrix inverse and and instead formulate the problem as something like a solution to a set of linear equations.
If the cost of engineering time is much more important than efficiency and the floating-point design fits in your chip and meets constraints on power, time, and cost of shipping parts, then staying in floating-point as much as possible is a fine choice.
If the constraints are not met or if your product would achieve advantage over your market competitors, like longer battery life or faster response times, then the engineering effort to make your algorithm more hardware efficient can be the difference between success and failure. For this case, Fixed-Point Designer provides many features like automatic collection of signal ranges and optimization searches for best scaling and wordlength that can greatly reduce the engineering effort needed.

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