Why does Simulink Design Verifier only find dead logic when I swap the order of my logical operands?

I have the following Stateflow charts:

Chart 1:

Chart 2:

The only difference in these two charts, is that the order of the operands at the second transition are swapped. Simulink Design Verifier finds dead logic in Chart 2, but not in Chart 1.

Answer 1

[MathWorks Support Team]

The reason you are seeing this behaviour is due to logical short-circuiting. See the following documentation page on logical short-circuiting for more details:

https://www.mathworks.com/help/matlab/ref/shortcircuitand.html

There are only two ways by which we can reach the second transition: if

Input1 != SomeNumber

, or if Inputs 2, 3 and 4 are

all false

.

Case 1: Input1 == SomeNumber

In the case that Input1 == SomeNumber, then Inputs 2, 3 and 4 must all be false. In this case, the second transition has to be true. In this specific case, the logic could be considered 'dead' in both charts.

Case 2: Input1 != SomeNumber

This is the case that sets the two charts apart. In this case, Inputs 2, 3 and 4 can be any combination of true and false.

In Chart 1, we first check whether Inputs 2, 3 and 4 are true, and since they can be in any combination of true and false, it is possible for us to reach of all the logic in this transition. For this reason, the logic is not considered 'dead'.

In Chart 2, however, logical short-circuiting kicks in because we check whether 

Input1 == SomeNumber

, which is false. We therefore will never reach the logic that follows and the logic is considered 'dead'.