To what degree are MathWorks drivers and libraries involved in the new ADI libiio based Linux images for Zynq + AD9361 targets?

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This is a question related to 19.2.1 version of:
Communications Toolbox Support Package for USRP Embedded Series Radio
Communications System Toolbox Support Package for Xilinx Zynq-Based Radio
Embedded Coder Support Package for Xilinx Zynq-7000 Platform
Where ADI's libiio drivers replace MW proprietary drivers, in particular for DMA/ AXI-stream communication through the Programmable Logic/FPGA.
From documentation it seems likely that the ADI libiio takes over all interfacing between SW on the Linux/ARM and both FPGA IP's, the ADI RF chip and also other peripherals.
Is this the case or is there more to it?
In the reference FPGA design for libiio distributed with "Communications Toolbox Support Package for USRP Embedded Series Radio", we can still see MW IP's (mainly some clock net manipulation and bypass muxing of user IP) if we look in the generated Vivado project.
Does this mean that there exists corresponding (to the PL/FPGA reference design) SW or kernel components made by MW necessary for a running SW/FPGA system on the Zynq?
So that the only Linux image that will work with the MW reference top level design is the corresponding image from the Support Package?
Can you please provide some structural/version details?
When moving to 2019b and libiio, can we expect all functionality available for a user SW application running on target (MW SD card from support package) to be as described on ADI's iio webpages, for example
Or are there conditions/restrictions?
Best regards,

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Ousman Sadiq
Ousman Sadiq 2019년 12월 5일
Hi, Terje,
Let me try and clarify things here and see if that answers some of the questions you have posed.
For the following SDR support packages:
Communications Toolbox Support Package for USRP Embedded Series Radio
Communications System Toolbox Support Package for Xilinx Zynq-Based Radio
We are using libiio, and the IIO drivers provided by Analog Devices to communicate with the AD936x based RF chips. This includes the drivers which stream samples from the PL to the PS over a DMA engine.
At a user level (for the customer) we expose a subset of available RF properties and some MathWorks specific functionality (Bypass user logic) through our system objects and blocks (1, 2, 3, 4). These are almost identical between Xilinx Zynq-Based Radio and USRP Embedded Series Radio.
If you want to config other (unexposed) RF properties then you will need to configure these manually using libiio, or by modifying the devicetree of the SD card images. Since we are using the Analog Devices drivers, all documented functionality should be available but there's potential for conflict if there are some properties which are being overridden by the MW blocks
For Embedded Coder Support Package for Xilinx Zynq-7000 Platform
This support package provide the target code generation infrastructure and blocks for the Zynq. It uses libiio to provide the AXI-Stream support for moving data between the PL and the PS. MathWorks authored IIO drivers are required to enable this functionality. This relies on having a HDL coder authored core (HW/SW co-design workflow) to co-ordinate the data movement.
AXI-Lite support does not use libiio at all.
I think what this means for you is that if you want to have AXI-Stream support there is a requirement to use the MW SD card images, and the HW/SW co-design workflow.
The other complicating factor is that our target code generation workflow (Monitor and Tune/External Mode, Build and Deploy) relies on cross-compilation with a sysroot generated via our MW SD card and a specific compiler toolchain
If you are only interested in using the the AD936x receiver and transmit functionality (without target code generation) then it should be possible to use the SD card images provided by Analog Devices. The only feature which won't have any effect is the Bypass user logic.
I hope that helps
Kind regards,
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Rimsha Javed
Rimsha Javed 2023년 6월 7일
We have a similar issue. We used HW/SW Co-Design workflow to generate bitstream for QPSK Transmitter and Recevier design for ADRV9361-z7035. Now we need to run it on a custom board by building OS through Petalinux. Though Mathworks provides option for custom board but since there are few limitations for the custom board. What should be the possible method to make Matlab design comptible forADI reference image.
Is it that we should go for Genrating HDL IP core individually rather than generating a whole bitstream and then route it in Vivado Design manually. Even it we do that way how to cater Axi Lite interface and ByPass TX RX IPs?

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