Can I get a delay equivalent to a fraction of a time step?

Hello everyone,

I want to add a delay (a fraction of a step time, I mean 0,054 ms) in a communication system simulation between a transmitter and a receiver. Transmitter is an integer (vector) to bit converter that receives a vector of ones and zeros (122 bits), like this:

Vector = [1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1]

(This is a CAN Protocol data frame, inlcuding stuffing bits)

That I get after Integer to Bit Converter:

That I get at two channels of scope block (with 4 time step - but I need a fraction of a time step):

Thanks in advance.

William

[Walter Roberson]

Not in discrete mode, you cannot. You would have to increase your sampling rate (decrease timestep) to be divisible by the desired delay.

In continuous mode, you could use a transfer function.

[William Diaz]

Thank you Walter for answering me.

I simulated using a TF, specifically using a LTI Block with parameters:

tf(10,[1 3 10],'inputdelay',2);

Nevertheless, It shows an error due to input vector width (122).

I tried a Variable Time Delay:

But Scope shows:

Could you give some advice with these both simulations.

Regards

William

[Walter Roberson]

Are the 122 bits to be processed in parallel, or is there an implicit bit timing between them? At the moment you are treating them as something to be handled in parallel. You should probably be converting them to a bit stream, and then the delays would be applied to the bit stream.

However, as soon as I see bit streams being sent around, I say that it is almost certainly a discrete time system for which using transfer functions to implement delays is not appropriate.

[William Diaz]

Hi Walter.

Actually, I want to process it by serial (bit by bit) because in a next system I need to simulate a wireless transmission, and I think it is possible if I get bit by bit of a 122x1 vector (this vector contains a data frame of CAN industrial protocol).

But I have to represent delays in order to simulate some conditions due to physical conection.

Is it possible with Simulink?

Regards

William

[Walter Roberson]

You really need a discrete-time system for that kind of work.

For discrete-time systems, you can only delay by a multiple of the sampling time for that section.

Possibly https://www.mathworks.com/help/dsp/ug/convert-sample-and-frame-rates-in-simulink.html will help.

[William Diaz]

Ok Walter, thank you. Let me check it and I'll comment you.

William

[William Diaz]

Walter, I have a question:

An important part of my research requires me to plot the frames, both on the transmitter and on the receiver side, with the intention of being able to visualize the delays between the frames of the two ends of the communication channel (sent frame and received frame).

If I work in a discrete system, could I visualize these delays in a simulink Scope? I mean, scope two dataframe and delay between them like an oscilloscope.

Something like this (delay = 4 bits, But I want a delay in micro seconds):

Note: Yellow = Original frame, Blue = delayed frame

[Walter Roberson]

Yes, with a discrete time system that should be possible... once it is worked out how to delay the bits for the appropriate time.

[William Diaz]

Hi Walter,

What about Serializer1D Block on Simulink to serilize a dataframe bitstream. Something like this:

Regards.

William

[Walter Roberson]

It looks to me as if Serializer1D is an HDL Toolbox function. Are you using HDL ?

[William Diaz]

No, I'm not using HDL.

But, could I use this block to serialize the 122x1 vector and apply:

• Delay (this gives a 8-bits vector, the LSB has the secuence of the serialized data)
• After the delay block, I want to count the number of bits after the firts zero bit (start of frame) in order to confirm the dataframe is correct (Can I do this using a function with the specific code?).

This is the simulation system (without the specific counter block):

And this is the Logic Analizer and the Scope plots (respectively):

Note: There is a 1 second delay.

[Walter Roberson]

I do not think you can use Serializer 1D except when you are targetting FPGA / HDL.

[William Diaz]

Ok, I understand your point.

Thank you Walter.