Generating VHDL code from MATLAB program using HDL generator

iam trying to generate vhdl code from matlab using HDL generator but iam facing error as "Signed input data type is not supported for division with Floor RoundMode".the above mentioned error coming near line "h1 =mod(x,752)", where x is unsigned integer.if i fix x value its generating properly.can any one tell me what is the problem here

Answer 1

[Bharath Venkataraman]

Is there a pattern to how x gets its value that you can utilize here? For example, if x is incremented by 1 all the time, or only crosses over 752 but not 752*2, you can make the code and the resultant HDL more efficient.

[nithin surabhi]

x get values from equation x=(19*m)+temp_const+1;

where m is 0 to 751;

temp constant can be 0 or 1 or 2 or 1000(depends of m).

[Bharath Venkataraman]

In this case, I suggest a simple lookup table to compute 19*m mod 752. It was unclear if temp_constant could be 1, 2 or 1000, or any value between 1-1000. Either way, you can compute temp_constant mod 752. Lastly, you can add the 3 values and if the value is > 752, use the value 752-value, otherwise use the value as is.