Hi , I am designing ADC for which I am giving clock signal, but I am curious about the parameter of clock signal that how can I set the rise and fall time of clock.
for example, with the following specs how much Trise and Tfall can be possible so that ADC can operate properly ?
Clock = 100MHz
Pulse width= 2.5n (duty cycle 25%)
Trise = ??
Tfall = ??
Actually, I want to know how much % of Trise and Tfall with respect to clock speed and pulse width. is there any ratio for this ?
could anyone please guide me with this query ?
Thanks

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카테고리

도움말 센터File Exchange에서 Clocks and Timers에 대해 자세히 알아보기

질문:

2019년 5월 19일

편집:

2019년 5월 19일

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