FPGA-in-the-Loop (FIL) Simulink Block Creation

Hello, I am having difficulty in creating a FIL block to perform median filtering on a data stream.

I have been using the "FILSimulinkWithVHTExample" example file and attempting to substitute the HDL Algorithm_fil1 block with one that is designated for my Xilinx FPGA. (See block with arrow pointing to it)

The FIL model, I'm assuming, looks something like this:

Where input port 1 is of type 'single', and 2-6 are Boolean. Output 1 is boolean, while output 2 is a "pixeldata". However,when I try to generate HDL code, I get an error

Does anyone have any advice or examples on making a working FIL block that is capable of performing an image processing algorithm? I am unable to deconstruct the provided FIL block to determine what its intial structure was.

Thanks.

Answer 1

[Bharath Venkataraman]

Does your HDL code handle single datatype pixel input? You may want to try it with the appropriate fixed-point pixel data that the HDL handles.

[andrew kurtz]

Yes, I think it does handle single datatype input, but my problem is coming from managing the pixel control input and multiplexing it into a single bus to be sent to the ctrl input of a sobel filter.

The methods I have tried so far:

• Using a multiplex block with 5 inputs and outputting that to the ctrl of a sobel filter
• Sending that multiplex output to a "signal specification" block with [1 5] as its dimensions
• Sending the input to a "pixels to frame" block with 5 inputs, sending that output to a "frame to pixels" with 2 outputs, and outputting that to the sobel filter

I am unsure how to go about doing this.

Thanks.

[Bharath Venkataraman]

I do not see where the edgedet2/Edge Detector block exists.

The HDL should have 6 ports, the first one for the pixel data and the next 5 being boolean inputs.

It will help if you are able to provide the model and HDL code.

[andrew kurtz]

Sorry, "edgedet2" is the Simulink file name. I am not sure what the Edge Detector is either.

I have attatched the Simulink model, and an image of it along with the error it generates.

This entire model is what I am hoping to compile into HDL to become a FIL block that does edge detection.

[Brian Ogilvie]

Hi Andrew,

It seems like you are trying to use FIL with a matrix input, which is not allowed. Recall that a matrix in Simulink can be a mathmatical matrix or more often in signal and video processing it can represent a collection of samples by channels. The FIL block outlaws this ambiguious input.

The FIL block does accept vectors of samples-over-time often called frames and that is key mechanism for rapid FIL simulation since the overhead cost is lower when using a large vector size. For video, an entire frame including the blanking intervals is a good choice for the vector size to make simulation faster. You can see that here under the heading "Modified FIL Model for Pixel Streaming"

What you really need to do is run the FIL Wizard in HDL Verifier to create the correct FIL block (doc here). This wizard works with either generated or hand-written HDL code and lets you set the port properties. That is the best way to get a FIL block your Xilinx median filter.

I would also mention that the Vision HDL Toolbox has median filters in various sizes and many other FPGA video processing functions that are platform independent.

If this doesn't answer your question completely, I think you should write again with your actual goal--is it simulation acceleration via FPGA? FIL does not always accelerate a design since there is overhead in moving data back and forth so care needs to be taken in the architecture of the design in that case.

-Brian

[andrew kurtz]

I have solved the problem:

My problem was the HDL compiler was unable to compile due to the "frame to pixel" output to the filter input due to the control signal being bussed incorrectly. I was using a standard MUX block, but was finally able to compile it using the "Pixel Control Bus Creator" block.

Sorry if my initial question was unclear.

Thanks.