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Developing dual cores application on Delfino F28379D MCU using simulink

조회 수: 11 (최근 30일)
Hello, I want to use Delfino F28379D for a dual core application but I can not as I have to choose which CPU to use on the Hardware Implementation tap.
Can I use Simulink for that, and how can I do inter-processor communication (IPC)??
Thankn in advance

답변 (1개)

Arun Munuswamy Sambandham
Arun Munuswamy Sambandham 2017년 7월 18일
Current support for F2837xD is with two model approach. You have to create two different models for each CPU core and establish a physical connection between two CPUs over SPI and share data (Note: requires additional external connections). Currently IPC is not supported by TI C2000 support package. May I know data type, data size you want to share and in what application? Your details will help us when we start supporting IPC in future.
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Mohamed Abdelaal
Mohamed Abdelaal 2017년 7월 18일
Hello, Thank you for your answer. I need to share about 10 floating point variables that i got from IMU and GPS. Can i write an Sfuntion with C-code that make the IPC? if so, how can i make it?
Arun Munuswamy Sambandham
Arun Munuswamy Sambandham 2017년 7월 19일
Yes you can use S-function, but easier way is to use System Objects. Refer this topic to create blocks https://www.mathworks.com/help/simulink/custom-blocks.html. The logic to use IPC is described in F2837xD IPC (Inter-Processor Communication) Device Driver documentation located in controlSUITE under the /device_support/F2837xD/ (VERSION)/doc/ directory. Hints: Create shared memory (Message RAM) for CPU1 and CPU2 from linker file, copy your variables into memory, before writing and reading use IPC flags to protect your write and read.
One more way is to add memory copy block in both models and insert custom code. For example, in CPU1 model add memory copy block as Input port, provide address of message RAM defined in linker for IPC (hex2dec('0003FC00')) as destination, then in Options insert custom code before mem write (set a IPC_FLAG) and after(Clear a IPC_FLAG). Use a similar protection logic in CPU2 memory copy block to read from this address.

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