Why do i get an an assertion error << Supply-side voltage must be greater than zero>> when trying to simulate a Dc-Dc converter ?

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Hello,
I'm trying to simulate a DC-DC converter supplied through diodes. I 'm using a very simple schematic, please see attached pdf. I get the following error message:
<<<<An error occurred while running the simulation and the simulation was terminated
Caused by:
At time 0.000000, an assertion is triggered. Supply-side voltage must be greater than zero. The assertion comes from:
Block path: Schema_pb_dcdc/DC-DC Converter
Assert location: (location information is protected)>>>
I feel that the problem comes from the delay introduced by diodes on the power supply lines to converter. How can I disable these assertion ? Or maybe force a dummy voltage at start time to override the path delay through diodes from voltage source to converter ? And so, satisfy the assertion ?
Best regards,
Thierry
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FELIX NATARAJA
FELIX NATARAJA 2022년 9월 18일
Hello Thierry,
Did you manage to find the answer to this ? I'm having the same problem with my modelling.
Regards
Felix

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Joel Van Sickel
Joel Van Sickel 2022년 9월 19일
Hello,
sorry for the late response, as this won't be useful to you, but the question got popped up again because of another user's comment. For the sake of answering future questions, here is the response. The basic DC/DC converter model used in this examples is what we call a "behavioral" model of a dc/dc converter. It is a simplified model that acts like a converter, but doesn't implement the physics or full feedback control loop. A detailed dc/dc converter would turn off when zero input voltage is applied. The original implementation of this model did not take input voltage into account, but this feature has been added. I believe it is specifically in 2022b. To work around this, the capacitor on the input of the dc/dc need to have a non-zero intial condition.
Regards,
Joel

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