SerDes toolbox Multiple lanes model

I achieved to build a Stimulus-TX-channel-RX-Eye Diagram UCIe 2.0 model on Simulink. Now i want to use a binary stimulus coming from a simple Verilog testbench model with the help of the HDL cosimulation blocks during runtime execution. Now i need to build a model with multiple lanes in which a single Stimulus-TX-channel-RX-Eye Diagram represents a single lane. I don't have access to Signal Integrity toolbox to model multiple lanes so i wanted to know fi there is any way to implement a multiple lanes model to analyze lanes channel behavior on runtime.

Answer 1

[Broy]

Hi @Jonathan,

I understand you are looking to scale your single-lane UCIe 2.0 model into a multi-lane system using a Verilog-based stimulus, but you do not have the Signal Integrity Toolbox to automatically analyze multiple lanes and crosstalk.

Here are two possible workarounds:

• Use the HDL Cosimulation to import your binary stimulus from the Verilog testbench.
• Wrap your existing Single-Lane model into a Simulink Subsystem or a Referenced Model. You can then instantiate this block N times to represent N lanes.

Here are some relevant documentation you can use:

• https://www.mathworks.com/help/releases/R2025b/hdlverifier/gs/hdl-cosimulation.html
• https://www.mathworks.com/help/releases/R2025b/simulink/model-reference.html

I hope it is helpful.