What is SLDV's option "Use strict propagation conditions"?

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I want to know the function of the "Use strict propagation conditions" option in Simulink Design Verifier.
I would appreciate it if you could explain using the attached model(R2023a).

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MathWorks Support Team
MathWorks Support Team 2025년 6월 18일
BLOT:
While EMCDC (Enhanced MCDC Coverage in Simulink Design Verifier) generates observable test cases, 'Use Strict Propagation' setting controls 'how far' the impact of a signal is propagated within design without getting masked by other computations.
Thus, the setting will have a 'qualitative' impact on the generated tests. And the generated tests will have better observability when the setting is ON than OFF. On the flip side, generating such tests in the former case is complex. 
Details:
Specifically, when 'Use strict propagation' setting is OFF - the impact propagation of a signal stops at soon as the boundary of the atomic subsystem is encountered in the path. Whereas the propagation continues within the atomic subsystem when the setting is ON. 
The following two screenshots for the attached example make this clear.
The below screenshots are obtained by (1) setting EMCDC mode as coverage setting in SLDV (2) Once the analysis is complete - inspecting the results for top level switch block by clicking the 'inspect' link. This link launches the Slicer and the Slicer highlighting helps to understand the extent of the signal propagation.
As you see, when strict propagation is disabled, impact of switch block is observed at its boundary (see the highlighting stops at 'Detection' point which is output of switch block. 
If 'Strict Propagation is disabled': 
If 'Strict Propagation is enabled' :
The propagation of signal continues, and impact of switch block is propagated inside atomic subsystem and to the output port. See how the values of all inputs are different to confirm the propagation path.


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